AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 32

• Manufacturer Part Number: AT91SAM7S321-AU
• Description: IC ARM7 MCU FLASH 32K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S321-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, I2S, SPI, SSC, TWI, UART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 10 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.5
9.6
9.7
32
Debug Unit
Periodic Interval Timer
Watchdog Timer
AT91SAM7S Series Summary
Note:
• Comprises:
• Two-pin UART
• Debug Communication Channel Support
• Chip ID Registers
• 20-bit programmable counter plus 12-bit interval counter
• 12-bit key-protected Programmable Counter running on prescaled SCLK
• Provides reset or interrupt signals to the system
• Counter may be stopped while the processor is in debug state or in idle mode
– One two-pin UART
– One Interface for the Debug Communication Channel (DCC) support
– One set of Chip ID Registers
– One Interface providing ICE Access Prevention
– Implemented features are compatible with the USART
– Programmable Baud Rate Generator
– Parity, Framing and Overrun Error
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
– Identification of the device revision, sizes of the embedded memories, set of
– Chip ID is 0x270B0A40 for AT91SAM7S512 Rev A and B
– Chip ID is 0x270D0940 for AT91SAM7S256 Rev A
– Chip ID is 0x270B0941 for AT91SAM7S256 Rev B
– Chip ID is 0x270B0942 for AT91SAM7S256 Rev C
– Chip ID is 0x270C0740 for AT91SAM7S128 Rev A
– Chip ID is 0x270A0741 for AT91SAM7S128 Rev B
– Chip ID is 0x270A0742 for AT91SAM7S128 Rev C
– Chip ID is 0x27090540 for AT91SAM7S64 Rev A
– Chip ID is 0x27090543 for AT91SAM7S64 Rev B
– Chip ID is 0x27090544 for AT91SAM7S64 Rev C
– Chip ID is 0x27080342 for AT91SAM7S321 Rev A
– Chip ID is 0x27080340 for AT91SAM7S32 Rev A
– Chip ID is 0x27080341 for AT91SAM7S32 Rev B
– Chip ID is 0x27050241 for AT9SAM7S161 Rev A
– Chip ID is 0x27050240 for AT91SAM7S16 Rev A
peripherals
Refer to the errata section of the datasheet for updates on chip ID.
6175IS–ATARM–30-Aug-10