PIC18C442-I/PT Microchip Technology, PIC18C442-I/PT Datasheet - Page 58

• Manufacturer Part Number: PIC18C442-I/PT
• Description: IC MCU OTP 8KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
5.1
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• TBLPTR registers
• TABLAT register
• RCON register
REGISTER 5-1:
DS39026C-page 56
Control Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCON REGISTER (ADDRESS: FD0h)
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable bit
1 = Enable TBLWT to internal program memory
0 = Disable TBLWT to internal program memory.
Note:
Unimplemented: Read as '0'
RI: RESET Instruction Flag bit
1 = No RESET instruction occurred
0 = A RESET instruction occurred
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset or POR Reset occurred
0 = A Brown-out Reset or POR Reset occurred
Legend:
R = Readable bit
- n = Value at POR reset
R/W-0
IPEN
(must be set in software after a Brown-out Reset occurs)
Only cleared on a POR or MCLR Reset.
This bit has no effect on TBLWTs to external program memory.
R/W-0
LWRT
U-0
—
W = Writable bit
’1’ = Bit is set
R/W-1
RI
5.1.1
The LWRT bit specifies the operation of Table Writes to
internal memory when the V
MCLR pin. When the LWRT bit is set, the controller
continues to execute user code, but long Table Writes
are allowed (for programming internal program mem-
ory) from user mode. The LWRT bit can be cleared only
by performing either a POR or MCLR Reset.
R/W-1
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
TO
RCON REGISTER
R/W-1
PD
2001 Microchip Technology Inc.
PP
voltage is applied to the
x = Bit is unknown
R/W-0
POR
R/W-0
BOR
bit 0