PIC16F876A-I/SS Microchip Technology, PIC16F876A-I/SS Datasheet - Page 6

• Manufacturer Part Number: PIC16F876A-I/SS
• Description: IC MCU FLASH 8KX14 EE 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F876A-I/SS

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Data Rom Size: 256 B
• Height: 1.75 mm
• Length: 10.2 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 5.3 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOPAC164020 - MODULE SKT PROMATEII 44TQFPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / Rohs Status: Details
• Other names: PIC16F876AI/SS

PIC16F87XA
2.4.2.1
After receiving this command, the program counter
(PC) will be set to 2000h. By then applying 16 cycles to
the clock pin, the chip will load 14 bits in a “data word,”
as described above, to be programmed into the config-
uration memory. A description of the memory mapping
schemes of the program memory for normal operation
and configuration mode operation is shown in
Figure 2-1. After the configuration memory is entered,
the only way to get back to the user program memory
is to exit the Program/Verify Test mode by taking MCLR
low (V
2.4.2.2
After receiving this command, the chip will load one
word (with 14 bits as a “data word”) to be programmed
into user program memory when 16 cycles are applied.
A timing diagram for this command is shown in
Figure 6-1.
2.4.2.3
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied.
However, the data memory is only 8-bits wide, and
thus, only the first 8 bits of data after the Start bit will be
programmed into the data memory. It is still necessary
to cycle the clock the full 16 cycles in order to allow the
internal circuitry to reset properly. The data memory
contains
code-protected, the data is read as all zeros. A timing
diagram for this command is shown in Figure 6-2.
2.4.2.4
After receiving this command, the chip will transmit
data bits out of the program memory (user or configu-
ration) currently accessed, starting with the second ris-
ing edge of the clock input. The RB7 pin will go into
Output mode on the second rising clock edge, and it
will revert back to Input mode (high-impedance) after
the 16th rising edge. A timing diagram of this command
is shown in Figure 6-3.
2.4.2.5
After receiving this command, the chip will transmit
data bits out of the data memory, starting with the sec-
ond rising edge of the clock input. The RB7 pin will go
into Output mode on the second rising edge, and it will
revert back to Input mode (high-impedance) after the
16th rising edge. As previously stated, the data mem-
ory is 8-bits wide, and therefore, only the first 8 bits that
are output are actual data. A timing diagram for this
command is shown in Figure 6-4.
2.4.2.6
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 6-5.
DS39589C-page 6
IL
).
up
Load Configuration
Load Data for Program Memory
Load Data for Data Memory
Read Data from Program Memory
Read Data from Data Memory
Increment Address
to
256
bytes.
If
the
Advance Information
device
is
2.4.2.7
Eight locations must be loaded before every
‘Begin Erase/Programming’ command. After this
command is received and decoded, eight words of
program memory will be erased and programmed with
the values contained in the program data latches. The
PC address will decode which eight words are pro-
grammed. The lower three bits of the PC are ignored,
so if the PC points to address 003h, then all eight
locations from 000h to 007h are written.
An internal timing mechanism executes an erase
before write. The user must allow the combined time
for erase and programming, as specified in the electri-
cal specs, for programming to complete. No ‘End
Programming’ command is required.
1.
2.
This command can be used to perform programming
over the entire V
A timing diagram for this command is shown in
Figure 6-6.
2.4.2.8
This command is similar to the ‘Erase/Programming
Cycle’ command, except that a word erase is not
done, and the internal timer is not used. Programming
of program and data memory will begin after this com-
mand is received and decoded. The user must allow
the time for programming, as specified in the electrical
specs, for programming to complete. An ‘End
Programming’ command is required.
The internal timer is not used for this command, so the
‘End Programming’ command must be used to stop
programming.
1.
2.
A timing diagram for this command is shown in
Figure 6-7.
Note:
Note 1: The code-protect bits cannot be erased
If the address is pointing to user memory, the
user memory alone will be affected.
If the address is pointing to the physically imple-
mented test memory (2000h - 201Fh), test mem-
ory will be written. The configuration word will not
be written unless the address is specifically
pointing to 2007h.
If the address is pointing to user memory, the
user memory alone will be affected.
If the address is pointing to the physically imple-
mented test memory (2000h - 201Fh), the test
memory will be written. The configuration word
will not be written unless the address is
specifically pointing to 2007h.
2: All Begin Erase/Programming operations
Begin Programming Only operations must
take place at the 4.5V to 5.5V V
with this command.
can take place over the entire V
Begin Erase/Program Cycle
Begin Programming Only
DD
range of the device.
 2010 Microchip Technology Inc.
DD
DD
range.
range.