PIC16F876A-I/SS Microchip Technology, PIC16F876A-I/SS Datasheet - Page 5

IC MCU FLASH 8KX14 EE 28SSOP

PIC16F876A-I/SS

Manufacturer Part Number
PIC16F876A-I/SS
Description
IC MCU FLASH 8KX14 EE 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F876A-I/SS

Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC16F
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Data Rom Size
256 B
Height
1.75 mm
Length
10.2 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4 V
Width
5.3 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164307 - MODULE SKT FOR PM3 28SSOPAC164020 - MODULE SKT PROMATEII 44TQFPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Lead Free Status / Rohs Status
 Details
Other names
PIC16F876AI/SS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F876A-I/SS
Manufacturer:
MICROCHI
Quantity:
7
Part Number:
PIC16F876A-I/SS
Manufacturer:
MICRO/PBF
Quantity:
8
Part Number:
PIC16F876A-I/SS
Manufacturer:
MIC
Quantity:
20 000
2.4
The Program/Verify mode is entered by holding pins
RB6 and RB7 low, while raising MCLR pin from V
V
pin does not effect programming. Low Voltage ICSP
Programming mode is entered by raising RB3 from V
to V
mode, the user program memory and the configuration
memory can be accessed and programmed in serial
fashion. The mode of operation is serial, and the mem-
ory accessed is the user program memory. RB6 and
RB7 are Schmitt Trigger inputs in this mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the RESET
state (the MCLR pin was initially at V
I/O are in the RESET state (high impedance inputs).
A device RESET will clear the PC and set the address
to ‘0’. The ‘Increment Address’ command will incre-
ment the PC. The ‘Load Configuration’ command will
set the PC to 2000h. The available commands are
shown in Table 2-1.
The normal sequence for programming eight program
memory words at a time is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The alternative sequence for programming one
program memory word at a time is as follows:
1.
2.
3.
4.
5.
6.
 2010 Microchip Technology Inc.
IHH
Note:
DD
Load a word at the current program memory
address using the ‘Load Data’ command.
Issue an ‘Increment Address’ command.
Load a word at the current program memory
address using the ‘Load Data’ command.
Repeat Step 2 and Step 3 six times.
Issue a ‘Begin Programming’ command to begin
programming.
Wait tprog (about 1 ms).
Issue an ‘End Programming’ command.
Increment to the next address.
Repeat this sequence as required to write
program and configuration memory.
Set a word for the current memory location using
the ‘Load Data’ command.
Issue a ‘Begin Programming Only’ command to
begin programming.
Wait tprog.
Issue an ‘End Programming’ command.
Increment to the next address.
Repeat this alternative sequence as required to
write program and configuration memory.
(high voltage). In this mode, the state of the RB3
, and then applying V
Program/Verify Mode
The OSC must not have 72 osc clocks
while the device MCLR is between V
V
IHH
.
DD
to MCLR. Once in this
IL
). This means all
Advance Information
IL
and
IL
to
IL
The address and program counter are reset to 0000h
by resetting the device (taking MCLR below V
re-entering Programming mode. Program and configu-
ration memory may then be read or verified using the
‘Read Data’ and ‘Increment Address’ commands.
2.4.1
Low Voltage ICSP Programming mode allows a
PIC16F87XA device to be programmed using V
only. However, when this mode is enabled by a config-
uration bit (LVP), the PIC16F87XA device dedicates
RB3 to control entry/exit into Programming mode.
When LVP bit is set to ‘1’, the low voltage ICSP pro-
gramming entry is enabled. Since the LVP configura-
tion bit allows low voltage ICSP programming entry in
its erased state, an erased device will have the LVP bit
enabled at the factory. While LVP is ‘1’, RB3 is dedi-
cated to low voltage ICSP programming. Bring RB3
and then, MCLR to V
All other specifications for high voltage ICSP apply.
To disable Low Voltage ICSP mode, the LVP bit must
be programmed to ‘0’. This must be done while entered
with the High Voltage Entry mode (LVP bit = ‘1’). RB3
is now a general purpose I/O pin.
2.4.2
The RB6 pin is used as a clock input pin, and the RB7
pin is used to enter command bits, and to input or out-
put data during serial operation. To input a command,
the clock pin (RB6) is cycled six times. Each command
bit is latched on the falling edge of the clock, with the
Least Significant bit (LSb) of the command being input
first. The data on RB7 is required to have a minimum
setup (tset1) and hold (thold1) time (see AC/DC speci-
fications), with respect to the falling edge of the clock.
Commands with associated data (read and load) are
specified to have a minimum delay (tdly1) of 1 s
between the command and the data. After this delay,
the clock pin is cycled 16 times, with the first cycle
being a Start bit (0) and the last cycle being a Stop bit
(0). Data is transferred LSb first.
During a read operation, the LSb will be transmitted
onto RB7 on the rising edge of the second cycle, and
during a load operation, the LSb will be latched on the
falling edge of the second cycle. A minimum 1 s delay
(tdly2) is specified between consecutive commands.
All commands and data words are transmitted LSb first.
The data is transmitted on the rising edge, and latched
on the falling edge of the clock. To allow decoding of
commands and reversal of data pin configuration, a
time separation of at least 1 s (tdly1) is required
between a command and a data word, or another
command.
The available commands are described in the following
paragraphs and listed in Table 2-1.
LOW VOLTAGE ICSP
PROGRAMMING MODE
SERIAL PROGRAM/VERIFY
OPERATION
PIC16F87XA
DD
to enter Programming mode.
DS39589C-page 5
IL
) and
DD

Related parts for PIC16F876A-I/SS