AT89C5131A-TISUL Atmel, AT89C5131A-TISUL Datasheet - Page 109

• Manufacturer Part Number: AT89C5131A-TISUL
• Description: MCU 8051 32K FLASH USB 28-SOIC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-TISUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Total Internal Ram Size: 1.25KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SOIC
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 54. Format and State in the Slave Receiver Mode
4338F–USB–08/07
Reception of the own
slave address and one or
more data bytes. All are
acknowledged.
Last data byte received
is not acknowledged.
Arbitration lost as master
and addressed as slave
Reception of the general call
address and one or more data
bytes.
Last data byte received is
not acknowledged.
Arbitration lost as master and
addressed as slave by general call
From master to slave
From slave to master
S
General Call
SLA
Data
n
W
A
70h
78h
60h
68h
A
A
A
A
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
Data
Data
80h
90h
A
A
Data
Data
80h
90h
88h
98h
A
A
A
A
P or S
P or S
P or S
P or S
A0h
A0h
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