DSPIC33FJ64MC510-E/PT Microchip Technology, DSPIC33FJ64MC510-E/PT Datasheet - Page 327

• Manufacturer Part Number: DSPIC33FJ64MC510-E/PT
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC510-E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TFQFP
• For Use With: AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

APPENDIX A: REVISION HISTORY
Revision A (June 2007)
Initial release of this document.
Revision B (March 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE A-1:
© 2009 Microchip Technology Inc.
Section 3.0 “Memory Organization”
Section 5.0 “Reset”
Section 7.0 “Direct Memory Access (DMA)” Updated the table cross-reference in Note 2 in the DMAxREQ
Section Name
MAJOR SECTION UPDATES
dsPIC33FJXXXMCX06/X08/X10
Updated Change Notification Register Map table title to reflect
application with dsPIC33FJXXXMCX10 devices (Table 3-2).
Added Change Notification Register Map tables (Table 3-3 and
Table 3-4) for dsPIC33FJXXXMCX08 and dsPIC33FJXXXMCX06
devices, respectively.
Updated SFR names in 8-Output PWM Register Map (Table 3-9).
Updated SFR names in QEI Register Map (Table 3-10).
Updated the bit range for AD1CON3 (ADCS<7:0>) in the ADC1
Register Map and added Note 1 (Table 3-17).
Updated the bit range for AD2CON3 (ADCS<7:0>) in the ADC2
Register Map (Table 3-18).
Updated the Reset value for C1FEN1 (FFFF) in the ECAN1 Register
Map When C1CTRL1.WIN = 0 or 1 (Table 3-20).
Updated the Reset value for C2FEN1 (FFFF) in the ECAN2 Register
Map When C2CTRL1.WIN = 0 or 1 and updated the title to reflect
application for dsPIC33FJXXXMC708/710 devices (Table 3-23).
Updated the title for the ECAN2 Register Map When C2CTRL1.WIN
= 0 to reflect application toward dsPIC33FJXXXMC708/710 devices
(Table 3-24).
Updated the title for the ECAN2 Register Map When C2CTRL1.WIN
= 1 to reflect application with dsPIC33FJXXXMC708/710 devices
(Table 3-25).
Updated Reset value for TRISA (C6FF) and changed the bit 12 and
bit 13 values for all File Names to unimplemented in the PORTA
Register Map (Table 3-26).
Added PMD Register Map (Table 4-35).
Added POR and BOR references in Reset Flag Bit Operation
(Table 5-1).
register (Register 7-2).
Update Description
DS70287C-page 325