PIC24FJ64GA010-I/PT Microchip Technology, PIC24FJ64GA010-I/PT Datasheet - Page 8

• Manufacturer Part Number: PIC24FJ64GA010-I/PT
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA010-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 100-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240011, AC164127, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ128GA010 FAMILY
14. Module: PMP (Master Mode)
15. Module: RTCC
16. Module: RTCC
DS80471A-page 8
With the PMP in Master mode (MODE<1:0> = 11
or 10) with the increment/decrement feature
enabled (INCM<1:0> = 01 or 10), the address
may not automatically change when the PMDINx
register is read. This issue may occur when
multiple back-to-back reads are performed.
Work around
The PMP address will be generated correctly if a
minimum of one instruction cycle delay is inserted
between the back-to-back read operations of the
PMDINx register. A NOP instruction, or any other
instruction, is adequate.
Affected Silicon Revisions
An RTCC increment may be missed if an RTCC
update and an RTCC increment occur at the same
time, and updates are disallowed (RTCWREN = 0).
In this condition, the RTCC is not updated since the
RTCWREN bit is clear.
Work around
Prior to writing to the RTCVAL registers, verify that
the RTCSYNC bit is clear and the RTCWREN bit
is set. This ensures that the RTCC will be updated
and the update will not occur during an RTCC
increment.
Affected Silicon Revisions
The RTCC automatic calibration, stored in the
CAL<7:0> bits, is intended to be applied every
minute on the minute boundary. The calibration is
applied after the first minute but may not occur on
subsequent minute intervals.
Work around
Read
(RTCPTR<1:0> = 00) value after each minute.
This reinitializes the calibration circuit and allows
the calibration to be applied to the next minute
increment.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
and
A4
A4
A4
rewrite
C1
C1
C1
C2
C2
C2
the
SECONDS
17. Module: I
18. Module: I
In I
Acknowledge a write operation (R/W = 0) after a
Restart has been received. This sequence is
typically used to perform a slave transmit opera-
tion in 10-Bit Addressing mode (A10M = 1).
Attempting to perform a write operation after a
Restart may cause the peripheral to generate a
NACK and end the operation unexpectedly.
Work around
To perform an I
Figure 24-27 from Section 24. “Inter-Integrated
Circuit™ (I
Manual” (DS39702).
Affected Silicon Revisions
I
bit should be set) only when the system is Idle (i.e.,
when ACKEN, RCEN, PEN, RSEN and SEN all
equal zero). It should not be possible to set the
RCEN bit when the system is not Idle; however,
the RCEN bit can be set under this circumstance.
Work around
Wait for the system to become Idle before setting
the RCEN bit. Verify that the following bits are
clear:
ACKEN, RCEN, PEN, RSEN and SEN.
Affected Silicon Revisions
2
A2
C Receive mode should be enabled (i.e., RCEN
A2
X
X
2
C Slave mode, the I
A3
A3
2
2
2
C™)” in the “PIC24F Family Reference
C (Slave Mode)
C
A4
A4
2
© 2009 Microchip Technology Inc.
C slave transmit, refer to
C1
C1
2
C2
C2
C peripheral may not