PIC24FJ64GA010-I/PT Microchip Technology, PIC24FJ64GA010-I/PT Datasheet - Page 18

• Manufacturer Part Number: PIC24FJ64GA010-I/PT
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA010-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 100-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240011, AC164127, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ128GA010 FAMILY
60. Module: SPI (Framed SPI Modes)
61. Module: SPI (Enhanced Mode)
DS80471A-page 18
Framed SPI modes, as described in the device data
sheet, are not supported. When using the module,
verify the FRMEN bit (SPIxCON2<15>) is cleared.
All other SPI modes function as described.
Work around
None.
Affected Silicon Revisions
SPI
(SPIBEN = 1) may set the interrupt flag, SPIxIF,
before the last bit has been transmitted from the
shift register. This issue only affects one of the
eight interrupt modes, SISEL<2:0> = 101, which
generates an interrupt when the last bit has shifted
out of the shift register, indicating the transfer is
complete. All other interrupt modes in Enhanced
Buffer mode work as described in the device data
sheet.
Work around
Multiple work arounds are available. Select
another
SISEL<2:0> bits in the SPIxSTAT register. A com-
parable mode is to generate an interrupt when the
FIFO is empty (SISEL<2:0> = 110). Another
option is to monitor the SRMPT bit (SPIxSTAT<7>)
to determine when the shift register is empty.
Affected Silicon Revisions
A2
A2
operating
A3
A3
Buffer
A4
A4
in
Interrupt
C1
C1
X
X
Enhanced
C2
C2
X
X
mode
Buffer
using
mode
the
62. Module: Core (Code Protection)
When general segment code protection has been
enabled (GCP Configuration bit is programmed),
applications are unable to write to the first
512 bytes of the program memory space (0000h
through 0200h). In applications that may require
the interrupt vectors to be changed during run
time, such as bootloaders, modifications to the
interrupt vector tables will not be possible.
Work around
Create two new interrupt vector tables, one each
for the IVT and AIVT, in an area of program space
beyond the affected region. Map the addresses in
the old vector tables to the new tables. These new
tables can then be modified as needed to the
actual addresses of the ISRs.
Affected Silicon Revisions
A2
A3
A4
© 2009 Microchip Technology Inc.
C1
X
C2