PIC18F2423-I/SO Microchip Technology, PIC18F2423-I/SO Datasheet - Page 41
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PIC18F2423-I/SO
Manufacturer Part Number
PIC18F2423-I/SO
Description
IC PIC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2423-ISP.pdf
(54 pages)
2.PIC18F2423-ISP.pdf
(8 pages)
3.PIC18F2423-ISP.pdf
(34 pages)
4.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18F2423-I/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Height
2.31 mm
Length
17.9 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
7.5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
FIGURE 4-4:
TABLE 4-2:
© 2009 Microchip Technology Inc.
130
131
132
135
137
Note 1:
Param
No.
Note 1:
A/D CLK
A/D DATA
SAMPLE
2:
3:
4:
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
DIS
2:
GO
Q4
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
(1)
If the A/D clock source is selected as RC, a time of T
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D CONVERSION REQUIREMENTS
A/D Clock Period
Conversion Time
(not including acquisition time)
Acquisition Time
Switching Time from Convert → Sample
Discharge Time
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
11
(3)
to V
SS
10
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
or V
PIC18F2423/2523/4423/4523
OLD_DATA
SS
9
(2)
to V
. . .
SAMPLING STOPPED
CY
DD
is added before the A/D clock starts. This allows the SLEEP instruction
). The source impedance (R
CY
. . .
130
131
cycle.
Min
0.8
1.4
1.4
0.2
13
—
—
—
3
(Note 4)
12.5
25.0
Max
14
—
—
1
3
2
(1)
(1)
Units
T
1
μs
μs
μs
μs
μs
μs
AD
S
) on the input channels is 50Ω.
T
V
T
A/D RC mode
V
OSC
OSC
DD
DD
0
AD
= 3.0V;
= 3.0V; A/D RC mode
based, V
based, V
clock divider.
NEW_DATA
DONE
Conditions
T
DS39755C-page 41
CY
REF
REF
≥ 3.0V
full range