PIC18F2423-I/SO Microchip Technology, PIC18F2423-I/SO Datasheet
PIC18F2423-I/SO
Specifications of PIC18F2423-I/SO
Related parts for PIC18F2423-I/SO
PIC18F2423-I/SO Summary of contents
Page 1
... PIC18F2423/2523/4423/4523 Microcontrollers with 12-Bit A/D © 2007 Microchip Technology Inc. 28/40/44-Pin, Enhanced Flash and nanoWatt Technology Preliminary Data Sheet DS39755B ...
Page 2
... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... PIC18F4423 16K 8192 PIC18F4523 32K 16384 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Flexible Oscillator Structure: • Four Crystal modes MHz • 4x Phase Lock Loop (available for crystal and internal oscillators) • Two External RC modes MHz • Two External Clock modes MHz • ...
Page 4
... I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. DS39755B-page /RE3 REF REF (3) 9 /RA7 20 (3) 19 /RA6 ( -/CV 1 REF 21 + REF PIC18F2423 PIC18F2523 (3) /RA7 6 16 (3) /RA6 Preliminary RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 (2) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA (2) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/ © 2007 Microchip Technology Inc. ...
Page 5
... RB3 is the alternate pin for CCP2 multiplexing. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 /RE3 ...
Page 6
... PIC18F2423/2523/4423/4523 Pin Diagrams (Cont.’d) (1) 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 Note recommended to connect the bottom pad of QFN package parts RB3 is the alternate pin for CCP2 multiplexing. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “ ...
Page 7
... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 375 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 375 Index ................................................................................................................................................................................................. 377 The Microchip Web Site ..................................................................................................................................................................... 387 Customer Change Notification Service .............................................................................................................................................. 387 Customer Support .............................................................................................................................................................................. 387 Reader Response .............................................................................................................................................................................. 388 PIC18F2423/2523/4423/4523 Product Identification System ............................................................................................................ 389 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 5 ...
Page 8
... PIC18F2423/2523/4423/4523 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
Page 9
... New Core Features 1.1.1 nanoWatt TECHNOLOGY All of the devices in the PIC18F2423/2523/4423/4523 family incorporate a range of features that can signifi- cantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90% ...
Page 10
... Section 26.0 “Electrical Characteristics” for time-out periods. DS39755B-page 8 1.3 Details on Individual Family Members Devices in the PIC18F2423/2523/4423/4523 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1 ...
Page 11
... MCLR (optional), WDT Programmable High/Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Instruction Set enabled Packages 28-pin PDIP 28-pin SOIC 28-pin QFN © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 PIC18F2523 DC – 40 MHz 16384 32768 8192 16384 768 1536 256 256 19 19 ...
Page 12
... PIC18F2423/2523/4423/4523 FIGURE 1-1: PIC18LF2423/2523 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory STKPTR (16/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine ...
Page 13
... RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Data Latch 8 Data Memory ( 3.9 Kbytes ) ...
Page 14
... PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18LF2423/2523 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP, QFN SOIC MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 9 6 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 7 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set ...
Page 15
... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
Page 16
... PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18LF2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, QFN SOIC RB0/INT0/FLT0/AN12 21 18 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 22 19 RB1 INT1 AN10 RB2/INT2/AN8 23 20 RB2 INT2 AN8 RB3/AN9/CCP2 24 21 RB3 AN9 (1) CCP2 RB4/KBI0/AN11 25 22 RB4 KBI0 AN11 ...
Page 17
... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
Page 18
... PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 13 32 OSC1 CLKI RA7 OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set ...
Page 19
... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTA is a bidirectional I/O port. 19 I/O TTL Digital I/O ...
Page 20
... PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/INT0/FLT0/AN12 33 9 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 34 10 RB1 INT1 AN10 RB2/INT2/AN8 35 11 RB2 INT2 AN8 RB3/AN9/CCP2 36 12 RB3 AN9 (1) CCP2 RB4/KBI0/AN11 37 14 RB4 KBI0 AN11 ...
Page 21
... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTC is a bidirectional I/O port. 32 I/O ST Digital I/O ...
Page 22
... PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0/PSP0 19 38 RD0 PSP0 RD1/PSP1 20 39 RD1 PSP1 RD2/PSP2 21 40 RD2 PSP2 RD3/PSP3 22 41 RD3 PSP3 RD4/PSP4 27 2 RD4 PSP4 RD5/PSP5/P1B 28 3 RD5 PSP5 P1B RD6/PSP6/P1C ...
Page 23
... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTE is a bidirectional I/O port. 25 I/O ST Digital I/O ...
Page 24
... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 22 Preliminary © 2007 Microchip Technology Inc. ...
Page 25
... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
Page 26
... PIC18F2423/2523/4423/4523 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Osc. Crystal Tested: Type Freq kHz MHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized ...
Page 27
... EXT C > EXT © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit clock the device up to its highest rated frequency from a crystal oscillator. This may be ...
Page 28
... PIC18F2423/2523/4423/4523 2.6 Internal Oscillator Block The PIC18LF2423/2523/4423/4523 devices include an internal oscillator block which generates two different clock signals; either can be used as the micro- controller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
Page 29
... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘ ...
Page 30
... WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18LF2423/2523/4423/ 4523 devices Section 23.0 “Special Features of the CPU” for Configuration register details. PIC18F2423/2523/4423/4523 HSPLL, INTOSC/PLL 4 x PLL OSCTUNE<6> OSCCON<6:4> 8 MHz 111 ...
Page 31
... INTRC is providing the clock or INTOSC has just started and is not yet stable. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
Page 32
... PIC18F2423/2523/4423/4523 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction ...
Page 33
... Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 not require a device clock source (i.e., MSSP slave, PSP, INTn pins and others). Peripherals that may add significant current Section 26.2 “ ...
Page 34
... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 32 Preliminary © 2007 Microchip Technology Inc. ...
Page 35
... IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
Page 36
... PIC18F2423/2523/4423/4523 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
Page 37
... PRI_RUN RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 n-1 n (1) ...
Page 38
... PIC18F2423/2523/4423/4523 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, ...
Page 39
... These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.4 Idle Modes The Idle modes allow the controller’s CPU to be shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
Page 40
... PIC18F2423/2523/4423/4523 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
Page 41
... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execu- tion continues or resumes without branching (see Section 9.0 “ ...
Page 42
... PIC18F2423/2523/4423/4523 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped and • the primary clock source is not any of the LP, XT HSPLL modes ...
Page 43
... Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. 4.1 ...
Page 44
... PIC18F2423/2523/4423/4523 REGISTER 4-1: RCON: RESET CONTROL REGISTER (1) R/W-0 R/W-1 U-0 IPEN SBOREN — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
Page 45
... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 FIGURE 4- ...
Page 46
... PIC18F2423/2523/4423/4523 4.4 Brown-out Reset (BOR) PIC18LF2423/2523/4423/4523 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If ...
Page 47
... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
Page 48
... PIC18F2423/2523/4423/4523 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OSC1 OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR RISES BEFORE MCLR INTERNAL POR PWRT TIME-OUT OSC1 OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR RISES AFTER T ...
Page 49
... FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OSC1 OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 OSC1 cycles. T OST PLL © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 , PWRT T OST T PWRT T OST T PLL ≈ max. Preliminary RISE > ...
Page 50
... PIC18F2423/2523/4423/4523 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
Page 51
... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
Page 52
... PIC18F2423/2523/4423/4523 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices FSR1H 2423 2523 4423 FSR1L 2423 2523 4423 BSR 2423 2523 4423 INDF2 2423 2523 4423 POSTINC2 2423 2523 4423 POSTDEC2 2423 2523 4423 PREINC2 2423 2523 4423 PLUSW2 ...
Page 53
... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
Page 54
... PIC18F2423/2523/4423/4523 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR2 2423 2523 4423 PIR2 2423 2523 4423 PIE2 2423 2523 4423 2423 2523 4423 IPR1 2423 2523 4423 2423 2523 4423 PIR1 2423 2523 4423 2423 2523 4423 ...
Page 55
... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The PIC18F2423 and PIC18F4423 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. PIC18F4523 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions ...
Page 56
... PIC18F2423/2523/4423/4523 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
Page 57
... Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
Page 58
... PIC18F2423/2523/4423/4523 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
Page 59
... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
Page 60
... PIC18F2423/2523/4423/4523 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
Page 61
... GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
Page 62
... PIC18F2423/2523/4423/4523 FIGURE 5-5: DATA MEMORY MAP FOR PIC18LF2423/4423 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
Page 63
... Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR 3FFh ...
Page 64
... PIC18F2423/2523/4423/4523 FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING POINTS TO 0x02FF) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
Page 65
... Unimplemented registers are read as ‘0’. 3: This register is not available on 28-pin devices. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The SFRs can be classified into two sets: those asso- ciated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral func- tions. The Reset and Interrupt registers are described in their respective chapters, while the ALU’ ...
Page 66
... PIC18F2423/2523/4423/4523 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF — PCLATU — — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
Page 67
... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — — (1) RCON IPEN SBOREN — ...
Page 68
... PIC18F2423/2523/4423/4523 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte RCREG EUSART Receive Register TXREG EUSART Transmit Register TXSTA CSRC TX9 TXEN ...
Page 69
... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the bits in the STATUS register ...
Page 70
... PIC18F2423/2523/4423/4523 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
Page 71
... ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “ ...
Page 72
... PIC18F2423/2523/4423/4523 The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory ...
Page 73
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 000h 060h 080h Bank 0 100h Bank 1 through Bank 14 ...
Page 74
... PIC18F2423/2523/4423/4523 5.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
Page 75
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 76
... PIC18F2423/2523/4423/4523 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 77
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-x R/W-0 (1) FREE ...
Page 78
... PIC18F2423/2523/4423/4523 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
Page 79
... MOVFW TABLAT, W MOVF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 80
... PIC18F2423/2523/4423/4523 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP™ control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 81
... CFGS bit to access program memory; • set WREN to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...
Page 82
... PIC18F2423/2523/4423/4523 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D’64’ MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER, F BRA ...
Page 83
... MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ...
Page 84
... PIC18F2423/2523/4423/4523 TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Name Bit 7 Bit 6 TBLPTRU — — TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch INTCON GIE/GIEH PEIE/GIEL TMR0IE EECON2 ...
Page 85
... EEPROM. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program Flash or data EEPROM memory ...
Page 86
... PIC18F2423/2523/4423/4523 REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit 7 Legend Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory ...
Page 87
... BSF INTCON, GIE BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 88
... PIC18F2423/2523/4423/4523 7.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 23.0 “ ...
Page 89
... CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE WRERR WREN — ...
Page 90
... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 88 Preliminary © 2007 Microchip Technology Inc. ...
Page 91
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
Page 92
... PIC18F2423/2523/4423/4523 Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • (ARG1L • ...
Page 93
... Individual interrupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC bility mode, the interrupt priority bits for each source have no effect. INTCON< ...
Page 94
... PIC18F2423/2523/4423/4523 FIGURE 9-1: PIC18 INTERRUPT LOGIC SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts DS39755B-page 92 TMR0IF TMR0IE ...
Page 95
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit ...
Page 96
... PIC18F2423/2523/4423/4523 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 97
... This feature allows for software polling. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt, otherwise, an interrupt will occur as soon as interrupts are enabled. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 U-0 ...
Page 98
... PIC18F2423/2523/4423/4523 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request Flag registers (PIR1 and PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 99
... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘0’ ...
Page 100
... PIC18F2423/2523/4423/4523 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
Page 101
... Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 ...
Page 102
... PIC18F2423/2523/4423/4523 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 103
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 104
... PIC18F2423/2523/4423/4523 9.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 9-10: RCON: RESET CONTROL REGISTER (1) R/W-0 ...
Page 105
... BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 106
... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 104 Preliminary © 2007 Microchip Technology Inc. ...
Page 107
... PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch (LATA) register is also memory mapped. ...
Page 108
... PIC18F2423/2523/4423/4523 TABLE 10-1: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/ RA2 0 V -/CV REF REF 1 AN2 REF CV REF x RA3/AN3/V + RA3 REF 0 1 AN3 REF 1 RA4/T0CKI/C1OUT RA4 0 1 T0CKI 1 C1OUT 0 RA5/AN4/SS/ RA5 0 HLVDIN/C2OUT 1 AN4 ...
Page 109
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 110
... PIC18F2423/2523/4423/4523 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 111
... PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 I/O I/O Type O DIG LATB< ...
Page 112
... PIC18F2423/2523/4423/4523 TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB PORTB Data Latch Register (Read and Write to Data Latch) TRISB PORTB Data Direction Control Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP ...
Page 113
... Configuration bit, CCP2MX CONFIG3H). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input ...
Page 114
... PIC18F2423/2523/4423/4523 TABLE 10-5: PORTC I/O SUMMARY TRIS Pin Function Setting RC0/T1OSO/ RC0 0 T13CKI 1 T1OSO x T13CKI 1 RC1/T1OSI/CCP2 RC1 0 1 T1OSI x (1) CCP2 0 1 RC2/CCP1/P1A RC2 0 1 CCP1 0 1 (2) P1A 0 RC3/SCK/SCL RC3 0 1 SCK 0 1 SCL 0 1 RC4/SDI/SDA RC4 0 1 SDI 1 SDA 1 1 RC5/SDO ...
Page 115
... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary Reset Bit 1 ...
Page 116
... PIC18F2423/2523/4423/4523 10.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on 40/44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 117
... DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: These registers and/or bits are not implemented on 28-pin devices. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 (1) I/O I/O Type ...
Page 118
... PIC18F2423/2523/4423/4523 TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 PORTD RD7 RD6 LATD PORTD Data Latch Register (Read and Write to Data Latch) TRISD PORTD Data Direction Control Register TRISE IBF OBF (1) (1) CCP1CON P1M1 P1M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. ...
Page 119
... Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 120
... PIC18F2423/2523/4423/4523 REGISTER 10-1: TRISE REGISTER (40/44-PIN DEVICES ONLY) R-0 R-0 R/W-0 IBF OBF IBOV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IBF: Input Buffer Full Status bit word has been received and waiting to be read by the CPU ...
Page 121
... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 I/O I/O Type O DIG LATE< ...
Page 122
... PIC18F2423/2523/4423/4523 10.6 Parallel Slave Port Note: The Parallel Slave Port is only available on 40/44-pin devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is con- trolled by the 4 upper bits of the TRISE register (Register 10-1) ...
Page 123
... GIE/GIEH PEIE/GIEL TMR0IF PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 Bit 3 Bit 2 RD5 ...
Page 124
... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 122 Preliminary © 2007 Microchip Technology Inc. ...
Page 125
... Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 126
... PIC18F2423/2523/4423/4523 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
Page 127
... Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 128
... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 126 Preliminary © 2007 Microchip Technology Inc. ...
Page 129
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 130
... PIC18F2423/2523/4423/4523 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
Page 131
... PIC18FXXXX C1 T1OSI XTAL 32.768 kHz T1OSO C2 Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type 12.6 pF 6.0 pF) L Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 132
... PIC18F2423/2523/4423/4523 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
Page 133
... Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 134
... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 132 Preliminary © 2007 Microchip Technology Inc. ...
Page 135
... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
Page 136
... PIC18F2423/2523/4423/4523 13.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
Page 137
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 138
... PIC18F2423/2523/4423/4523 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 14-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger CCP1/CCP2 Select from T3CON<6,3> Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. ...
Page 139
... RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 140
... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 138 Preliminary © 2007 Microchip Technology Inc. ...
Page 141
... Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match (CCPxIF bit is set) 11xx = PWM mode © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. Note: Throughout this section and Section 16.0 “ ...
Page 142
... PIC18F2423/2523/4423/4523 15.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable in Capture and Compare modes. ...
Page 143
... Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear while changing the CCP mode to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
Page 144
... PIC18F2423/2523/4423/4523 15.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the ...
Page 145
... These bits are unimplemented on 28-pin devices; always maintain these bits clear. 2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 146
... PIC18F2423/2523/4423/4523 15.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: Clearing the CCPxCON register will force ...
Page 147
... CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 EQUATION 15-3: PWM Resolution (max) = Note: If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be cleared ...
Page 148
... PIC18F2423/2523/4423/4523 TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (2) RCON IPEN SBOREN (1) PIR1 PSPIF ADIF (1) PIE1 PSPIE ADIE (1) IPR1 PSPIP ADIP TRISB PORTB Data Direction Control Register TRISC PORTC Data Direction Control Register TMR2 Timer2 Register ...
Page 149
... PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of the ECCP module are the same as described for the standard CCP module ...
Page 150
... PIC18F2423/2523/4423/4523 In addition to the expanded range of modes available through the CCP1CON register and ECCP1AS register, the ECCP module has an additional register associated with Enhanced PWM operation and auto-shutdown features. It is: • ECCP1DEL (Dead-Band Delay) 16.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode ...
Page 151
... PR2 Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation ...
Page 152
... PIC18F2423/2523/4423/4523 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation ...
Page 153
... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 16.4.6 “Programmable Dead-Band Delay”). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Duty Cycle Period (1) Delay Delay Duty Cycle Period ...
Page 154
... PIC18F2423/2523/4423/4523 16.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown ...
Page 155
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 156
... PIC18F2423/2523/4423/4523 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F4X23 P1A P1B P1C P1D 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction. When the application firm- ware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
Page 157
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals Forward Period t1 ...
Page 158
... PIC18F2423/2523/4423/4523 16.4.6 PROGRAMMABLE DEAD-BAND DELAY Note: Programmable dead-band delay is not implemented in 28-pin devices with standard CCP modules. In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power ...
Page 159
... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 (1) (1) (1) PDC4 ...
Page 160
... PIC18F2423/2523/4423/4523 16.4.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 161
... Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 162
... PIC18F2423/2523/4423/4523 TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP TRISB PORTB Data Direction Control Register ...
Page 163
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
Page 164
... PIC18F2423/2523/4423/4523 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
Page 165
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
Page 166
... PIC18F2423/2523/4423/4523 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
Page 167
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 168
... PIC18F2423/2523/4423/4523 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
Page 169
... Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output ...
Page 170
... PIC18F2423/2523/4423/4523 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
Page 171
... PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. ...
Page 172
... PIC18F2423/2523/4423/4523 2 17 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing ...
Page 173
... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2 C™ MODE) R-0 R-0 ...
Page 174
... PIC18F2423/2523/4423/4523 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I ...
Page 175
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2 C™ MODE) R/W-0 R/W-0 ...
Page 176
... PIC18F2423/2523/4423/4523 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I bit 1 RSEN/ADMSK1: Repeated Start Condition Enable bit (1) In Master mode Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware Repeated Start condition Idle In Slave mode (7-Bit Address mode Address masking of ADD1 enabled ...
Page 177
... I C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All ...
Page 178
... PIC18F2423/2523/4423/4523 17.4.3.2 Address Masking Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt possible to mask more than one address bit at a time, which makes it possible to Acknowledge addresses in 7-bit mode and addresses in 10-bit mode (see Example 17-2) ...
Page 179
... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more detail. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.4.3.4 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 180
... PIC18F2423/2523/4423/4523 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39755B-page 178 Preliminary © 2007 Microchip Technology Inc. ...
Page 181
... FIGURE 17-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 179 ...
Page 182
... PIC18F2423/2523/4423/4523 2 FIGURE 17-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39755B-page 180 Preliminary © 2007 Microchip Technology Inc. ...
Page 183
... FIGURE 17-11: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 181 ...
Page 184
... PIC18F2423/2523/4423/4523 2 FIGURE 17-12: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39755B-page 182 Preliminary © 2007 Microchip Technology Inc. ...
Page 185
... FIGURE 17-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 183 ...
Page 186
... PIC18F2423/2523/4423/4523 17.4.4 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
Page 187
... DX SCL CKP WR SSPCONx © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-14) ...
Page 188
... PIC18F2423/2523/4423/4523 2 FIGURE 17-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39755B-page 186 Preliminary © 2007 Microchip Technology Inc. ...
Page 189
... FIGURE 17-16: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 187 ...
Page 190
... PIC18F2423/2523/4423/4523 17.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge ...
Page 191
... FIGURE 17-18: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condi- tion is complete ...
Page 192
... PIC18F2423/2523/4423/4523 2 17.4.6 Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
Page 193
... C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
Page 194
... PIC18F2423/2523/4423/4523 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the ...
Page 195
... FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the SCL line is sampled low before the SDA ...
Page 196
... PIC18F2423/2523/4423/4523 2 17.4 MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sam- pled low, the Baud Rate Generator is loaded with the contents of SSPADD< ...
Page 197
... WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowl- edge (ACK = 1) ...
Page 198
... PIC18F2423/2523/4423/4523 2 FIGURE 17-23: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39755B-page 196 Preliminary © 2007 Microchip Technology Inc. ...
Page 199
... FIGURE 17-24: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 197 ...
Page 200
... PIC18F2423/2523/4423/4523 17.4.12 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to gen- erate an Acknowledge, then the ACKDT bit should be cleared ...