ATMEGA128A-AUR Atmel, ATMEGA128A-AUR Datasheet - Page 170
ATMEGA128A-AUR
Manufacturer Part Number
ATMEGA128A-AUR
Description
MCU AVR 128K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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Manufacturer:
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19.3
19.3.1
19.3.2
19.4
8151H–AVR–02/11
SS Pin Functionality
Data Modes
Slave Mode
Master Mode
When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user
configured as an output, and the SPI is passive, which means that it will not receive incoming
data. Note that the SPI logic will be reset once the SS pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the following
actions:
Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI master
mode.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
1
ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
19-2
Table 1. CPOL and CPHA Functionality
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG
and
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
and
the SPI becoming a slave, the MOSI and SCK pins become inputs.
is set, the interrupt routine will be executed.
Figure
Table
2. Data bits are shifted out and latched in on opposite edges of the SCK signal,
19-3, as done below:
Sample (Falling)
Sample (Rising)
Leading edge
Setup (Falling)
Setup (Rising)
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing edge
ATmega128A
SPI mode
0
1
2
3
Figure
Table
170
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