PIC16LC926T-I/PT Microchip Technology, PIC16LC926T-I/PT Datasheet - Page 93
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PIC16LC926T-I/PT
Manufacturer Part Number
PIC16LC926T-I/PT
Description
IC MCU CMOS 20MHZ 8K W/LCD64TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC926T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
OTP
Ram Size
336 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
336 B
Interface Type
I2C, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC926T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
11.2
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver, such as a Microchip AY0438,
can be synchronized for segment data update to the
LCD frame.
FIGURE 11-7:
2001 Microchip Technology Inc.
COM0
COM1
COM2
COM3
T
T
LCD Interrupts
FWR
FINT
Frame
Boundary
= T
= (T
(T
FRAME
FWR
FWR
EXAMPLE WAVEFORMS AND INTERRUPT TIMING
IN QUARTER-DUTY CYCLE DRIVE
/(LMUX1:LMUX0 + 1) + T
/2 - (2T
/2 - (1T
CY
CY
+ 40 ns))
+ 40 ns))
1 Frame
minimum = 1.5(T
maximum = 1.5(T
CY
Preliminary
/2
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(T
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (T
must be written within T
controller will begin to access the data for the next
frame.
LCD
Interrupt
Occurs
FINT
FRAME
FRAME
), as shown in Figure 11-7. The LCD controller
T
FWR
/4) - (2T
/4) - (1T
T
FINT
PIC16C925/926
CY
CY
Controller Accesses
Next Frame Data
+ 40 ns)
+ 40ns)
Frame
Boundary
FWR
, as this is when the LCD
DS39544A-page 91
FWR
). New data
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V