DSPIC30F3013-20I/SP Microchip Technology, DSPIC30F3013-20I/SP Datasheet - Page 115
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DSPIC30F3013-20I/SP
Manufacturer Part Number
DSPIC30F3013-20I/SP
Description
IC DSPIC MCU/DSP 24K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(210 pages)
2.DSPIC30F2011-20ISO.pdf
(6 pages)
3.DSPIC30F3012-20ISO.pdf
(14 pages)
4.DSPIC30F3012-20ISO.pdf
(20 pages)
5.DSPIC30F2012-30ISO.pdf
(205 pages)
Specifications of DSPIC30F3013-20I/SP
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301320ISP
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F3012-20ISO PDF datasheet #3
- DSPIC30F3012-20ISO PDF datasheet #4
- DSPIC30F2012-30ISO PDF datasheet #5
- Current page: 115 of 205
- Download datasheet (3Mb)
The configuration procedures below give the required
setup values for the conversion speeds above 100
ksps.
16.7.1
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 16-1.
• Connect external V
• Set SSRC<2.0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Write the SMPI<3.0> control bits in the ADCON2
• Configure the ADC clock period to be:
• Configure the sampling time to be 1 T
FIGURE 16-3:
© 2006 Microchip Technology Inc.
the recommended circuit shown in Figure 16-2.
enable the auto convert option.
control bit in the ADCON1 register.
register for the desired number of conversions
between interrupts.
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
writing: SAMC<4:0> = 00001.
(14 + 1) x 200,000
200 KSPS CONFIGURATION
GUIDELINE
Note: C
1
Legend: C
VA
PIN
REF
Rs
12-BIT A/D CONVERTER ANALOG INPUT MODEL
value depends on device package and is not tested. Effect of C
+ and V
V
I leakage
R
R
C
ANx
T
PIN
IC
SS
HOLD
C
= 334 ns
PIN
REF
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
- pins following
dsPIC30F2011/2012/3012/3013
AD
V
by
DD
V
V
T
T
= 0.6V
= 0.6V
R
I leakage
IC
500 nA
250
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T
tion with the guidelines described above allows a con-
version speed of 200 ksps. See Example 16-1 for code
example.
16.8
The analog input model of the 12-bit ADC is shown in
Figure 16-3. The total sampling time for the A/D is a
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source impedance (R
(R
ance combine to directly affect the time required to
charge the capacitor C
ance of the analog sources must therefore be small
enough to fully charge the holding capacitor within the
chosen sample time. To minimize the effects of pin
leakage currents on the accuracy of the ADC, the max-
imum recommended source impedance, R
After the analog input channel is selected (changed),
this sampling function must be completed prior to start-
ing the conversion. The internal holding capacitor will
be in a discharged state prior to each sample opera-
tion.
IC
), and the internal sampling switch (R
Sampling
Switch
A/D Acquisition Requirements
R
SS
PIN
R
negligible if Rs
SS
V
SS
HOLD
C
= DAC capacitance
= 18 pF
S
HOLD
), the interconnect impedance
3 k
HOLD
) must be allowed to fully
. The combined imped-
AD
selection in conjunc-
2.5 k .
DS70139E-page 113
S
SS
, is 2.5 k .
) imped-
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