PIC16C773-I/SS Microchip Technology, PIC16C773-I/SS Datasheet - Page 94

• Manufacturer Part Number: PIC16C773-I/SS
• Description: IC MCU OTP 4KX14 A/D PWM 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C773-I/SS

• Program Memory Type: OTP
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Controller Family/series: PIC16C
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16C77X
8.2.18.17 BUS COLLISION DURING A STOP
Bus collision occurs during a STOP condition if:
a)
b)
FIGURE 8-40: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 8-41:
DS30275A-page 94
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
CONDITION
SDA
PEN
SCL
P
’0’
’0’
BUS COLLISION DURING A STOP CONDITION (CASE 2)
’0’
’0’
Assert SDA
T
SDA asserted low
BRG
T
BRG
Advance Information
T
BRG
T
BRG
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allow to float.
When the pin is sampled high (clock arbitration), the
baud rate generator is loaded with SSPADD<6:0> and
counts down to 0. After the BRG times out SDA is sam-
pled.
occurred. This is due to another master attempting to
drive a data ’0’. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs.
This is another case of another master attempting to
drive a data ’0’
If SDA is sampled low, a bus collision has
SCL goes low before SDA goes high
Set BCLIF
(Figure
T
BRG
T
BRG
8-40).
1999 Microchip Technology Inc.
’0’
’0’
SDA sampled
low after T
Set BCLIF
BRG
,