PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 347
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 347 of 496
- Download datasheet (5Mb)
23.6
When enabled, the HLVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
TABLE 23-1:
2010 Microchip Technology Inc.
HLVDCON
INTCON
IPR2
PIE2
PIR2
TRISA
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are unused by the HLVD module.
Name
Operation During Sleep
VDIRMAG
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIE
OSCFIF
TRISA7
Bit 7
REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
TRISA6
BGVST
Bit 6
C1IP
C1IE
C1IF
TRISA5
IRVST
C2IP
C2IE
Bit 5
C2IF
Preliminary
HLVDEN
TRISA4
INT0IE
EEIP
EEIE
Bit 4
EEIF
TRISA3
BCL1IP
BCL1IE
BCL1IF
23.7
A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.
RBIE
Bit 3
PIC18(L)F2X/4XK22
Effects of a Reset
TMR0IF
HLVDIP
HLVDIE
HLVDIF
TRISA2
Bit 2
HLVDL<3:0>
TMR3IP
TMR3IE
TMR3IF
TRISA1
INT0IF
Bit 1
CCP2IP
CCP2IE
CCP2IF
TRISA0
DS41412D-page 347
RBIF
Bit 0
on page
Values
Reset
343
128
124
154
115
119
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