ATMEGA644PV-10PQ Atmel, ATMEGA644PV-10PQ Datasheet - Page 295
![MCU AVR 64K FLASH 10MHZ 40-PDIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA644PV-10PQ
Manufacturer Part Number
ATMEGA644PV-10PQ
Description
MCU AVR 64K FLASH 10MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PV-10PQ
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8011O–AVR–07/10
Table 24-4.
Note:
Table 24-5.
Note:
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
Fuse High Byte
OCDEN
JTAGEN
SPIEN
WDTON
EESAVE
BOOTSZ1
BOOTSZ0
BOOTRST
Fuse Low Byte
CKDIV8
CKOUT
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
(1)
1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOOTSZ1..0 results in maximum Boot Size. See
3. See
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See
3. The CKOUT Fuse allow the system clock to be output on PORTB1. See
4. See
(3)
(4)
(4)
(3)
for details.
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sleep modes. This may increase the power consumption.
See
page 30
on page 38
Fuse High Byte
Fuse Low Byte
”WDTCSR – Watchdog Timer Control Register” on page 59
”System and Reset Characteristics” on page 331
”System Clock Prescaler” on page 38
for details.
Bit No
for details.
7
6
5
4
3
2
1
0
Bit No
7
6
5
4
3
2
0
1
Description
Enable OCD
Enable JTAG
Enable Serial Program and Data
Downloading
Watchdog Timer always on
EEPROM memory is preserved
through the Chip Erase
Select Boot Size (see
details)
Select Boot Size (see
details)
Select Reset Vector
Description
Divide clock by 8
Clock output
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
ATmega164P/324P/644P
for details.
Table 24-9
Table 24-9
for details.
for
for
Default Value
1 (unprogrammed, OCD
disabled)
0 (programmed, JTAG enabled)
0 (programmed, SPI prog.
enabled)
1 (unprogrammed)
1 (unprogrammed, EEPROM
not preserved)
0 (programmed)
0 (programmed)
1 (unprogrammed)
Default Value
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
1 (unprogrammed)
0 (programmed)
for details.
Table 23-7 on page 288
”Clock Output Buffer”
(2)
(2)
(1)
(2)
(2)
(2)
Table 6-1 on
(1)
(2)
295
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