ATMEGA644PV-10PQ Atmel, ATMEGA644PV-10PQ Datasheet - Page 111
![MCU AVR 64K FLASH 10MHZ 40-PDIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA644PV-10PQ
Manufacturer Part Number
ATMEGA644PV-10PQ
Description
MCU AVR 64K FLASH 10MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PV-10PQ
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13. 16-bit Timer/Counter1 with PWM
13.1
13.2
8011O–AVR–07/10
Features
Overview
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement.
Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
placement of I/O pins, see
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the
The PRTIM1 bit in
enable Timer/Counter1 module.
True 16-bit Design (that is, allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
”Register Description” on page
”PRR – Power Reduction Register” on page 48
”Pin Configurations” on page
132.
ATmega164P/324P/644P
2. CPU accessible I/O Registers, includ-
Figure
must be written to zero to
13-1. For the actual
111
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