ATMEGA644PV-10MU Atmel, ATMEGA644PV-10MU Datasheet - Page 308
ATMEGA644PV-10MU
Manufacturer Part Number
ATMEGA644PV-10MU
Description
MCU 8-BIT 64K ISP FLASH 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PV-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
10MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q3423944
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA644PV-10MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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24.8
24.8.1
8011O–AVR–07/10
Serial Downloading
Serial Programming Pin Mapping
Both the Flash and EEPROM memory arrays can be programmed using a serial programming
bus while RESET is pulled to GND. The serial programming interface consists of pins SCK,
MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
24-15 on page
SPI pins dedicated for the internal Serial Peripheral Interface - SPI.
Table 24-15. Pin Mapping Serial Programming
Figure 24-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
Symbol
MOSI
MISO
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
SCK
XTAL1 pin.
CC
- 0.3V < AVCC < V
308, the pin mapping for serial programming is listed. Not all packages use the
(PDIP-40)
Pins
PB5
PB6
PB7
MOSI
MISO
SCK
ck
ck
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8V - 5.5V
XTAL1
RESET
GND
(TQFP-44)
(1)
Pins
PB5
PB6
PB7
ATmega164P/324P/644P
AVCC
VCC
+1.8V - 5.5V
+1.8V - 5.5V
I/O
O
I
I
(2)
ck
ck
>= 12 MHz
>= 12 MHz
Serial Data out
Serial Data in
Description
Serial Clock
Table
308
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