ATMEGA644PV-10MU Atmel, ATMEGA644PV-10MU Datasheet - Page 272
ATMEGA644PV-10MU
Manufacturer Part Number
ATMEGA644PV-10MU
Description
MCU 8-BIT 64K ISP FLASH 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PV-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
10MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q3423944
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA644PV-10MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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22.6
8011O–AVR–07/10
ATmega164P/324P/644P Boundary-scan Order
Table 22-1
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port K is
scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan
chains for the analog circuits, which constitute the most significant bits of the scan chain regard-
less of which physical pin they are connected to. In
PXn. Control corresponds to FF1, PXn. Bit 4, bit 5, bit 6 and bit 7 of Port F is not in the scan
chain, since these pins constitute the TAP pins when the JTAG is enabled.
Table 22-1.
Bit Number
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
shows the Scan order between TDI and TDO when the Boundary-scan chain is
ATmega164P/324P/644P Boundary-scan Order
Signal Name
PB0.Data
PB0.Control
PB1.Data
PB1.Control
PB2.Data
PB2.Control
PB3.Data
PB3.Control
PB4.Data
PB4.Control
PB5.Data
PB5.Control
PB6.Data
PB6.Control
PB7.Data
PB7.Control
RSTT
ATmega164P/324P/644P
Figure
Module
Port B
Reset Logic (Observe Only)
22-3, PXn. Data corresponds to FF0,
272
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