AT32UC3B164-AUR Atmel, AT32UC3B164-AUR Datasheet - Page 529
AT32UC3B164-AUR
Manufacturer Part Number
AT32UC3B164-AUR
Description
MCU AVR32 64K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B164-AUR
Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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24.6.2
24.6.2.1
Figure 24-3. Functional View of the Channel Block Diagram
24.6.2.2
32059J–12/2010
PWM Channel
Block Diagram
Waveform Properties
Inputs from
Inputs from
Peripheral
generator
clock
Bus
divided clocks.
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the Mode reg-
ister (MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field
value in the Mode register (MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the Mode register are
cleared. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa-
tion is also true when the PWM master clock is turned off through the Power Manager .
Each of the
• A clock selector which selects one of the clocks provided by the clock generator described in
• An internal counter clocked by the output of the clock selector. This internal counter is
• A comparator used to generate events according to the internal counter value. It also computes
The different properties of output waveforms are:
• the internal clock selection. The internal channel counter is clocked by one of the clocks
Section
incremented or decremented according to the channel configuration and comparators events.
The size of the internal counter is
the PWMx output waveform according to the configuration.
provided by the clock generator described in the previous section. This channel parameter is
defined in the CPRE field of the CMRx register. This field is reset at 0.
Selector
Channel
Clock
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
F
F
clkB
CLK_PWM
CLK_PWM
24.6.1.
7
channels is composed of three blocks:
/8, F
/512, F
CLK_PWM
CLK_PWM
Counter
Internal
/16, F
/1024
CLK_PWM
20
bits.
/32, F
Comparator
CLK_PWM
CLK_PWM
/64, F
CLK_PWM
, F
CLK_PWM
/128, F
PWMx output
waveform
/2, F
AT32UC3B
CLK_PWM
CLK_PWM
/256,
/4,
529
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