AT32UC3B164-AUR Atmel, AT32UC3B164-AUR Datasheet - Page 210
![MCU AVR32 64K FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B164-AUR
Manufacturer Part Number
AT32UC3B164-AUR
Description
MCU AVR32 64K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B164-AUR
Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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18.8.2
Name:
Access Type:
Offset:
Reset Value:
• DLYBCS: Delay Between Chip Selects
• PCS: Peripheral Chip Select
• LLB: Local Loopback Enable
• MODFDIS: Mode Fault Detection
• PCSDEC: Chip Select Decode
32059J–12/2010
LLB
31
23
15
–
–
7
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default.
Otherwise, the following equation determines the delay:
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
0: Local loopback path disabled.
1: Local loopback path enabled (
LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.)
0: Mode fault detection is enabled.
1: Mode fault detection is disabled.
0: The chip selects are directly connected to a peripheral device.
1: The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
CSR0 defines peripheral chip select signals 0 to 3.
CSR1 defines peripheral chip select signals 4 to 7.
Delay Between Chip Selects
Mode Register
30
22
14
MR
Read/Write
0x04
0x00000000
–
–
6
-
29
21
13
–
–
5
-
=
DLYBCS
---------------------- -
CLKSPI
MODFDIS
28
20
12
–
–
4
DLYBCS
27
19
11
–
3
–
PCSDEC
26
18
10
–
2
PCS
PS
25
17
–
9
1
AT32UC3B
MSTR
24
16
–
8
0
210
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