ATMEGA168V-10PU Atmel, ATMEGA168V-10PU Datasheet - Page 35

• Manufacturer Part Number: ATMEGA168V-10PU
• Description: IC AVR MCU 16K 10MHZ 28DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA168V-10PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: 2-Wire, SPI, USART, Serial
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3 bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.11.1
2545E–AVR–02/05
Clock Prescale Register – CLKPR
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must befollowed to
change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operat-
ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application software must ensure that a sufficient division factor is chosen if
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Bit
Read/Write
Initial Value
CLKPR to zero.
6-14.
CLKPCE
R/W
7
0
R
6
–
0
R
5
–
0
R
4
–
0
CLKPS3
R/W
3
CLKPS2
See Bit Description
R/W
ATmega48/88/168
2
CLKPS1
R/W
1
CLKPS0
R/W
0
CLKPR
35