DSPIC33FJ12MC202-I/SP Microchip Technology, DSPIC33FJ12MC202-I/SP Datasheet - Page 64
![IC DSPIC MCU/DSP 12K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ12MC202-I/SP
Manufacturer Part Number
DSPIC33FJ12MC202-I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- DSPIC33FJ12MC202-IML PDF datasheet #4
- Current page: 64 of 288
- Download datasheet (5Mb)
dsPIC33FJ12MC201/202
6.1
The dsPIC33FJ12MC201/202 family of devices have
two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a POR or a BOR. On a cold
Reset, the FNOSC configuration bits in the FOSC
device configuration register selects the device clock
source.
A warm Reset is the result of all other Reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>)
(OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure 6-2.
1.
2.
TABLE 6-1:
DS70265D-page 62
FRC, FRCDIV16,
FRCDIVN
FRCPLL
XT
HS
EC
XTPLL
HSPLL
ECPLL
SOSC
LPRC
Note 1:
Oscillator Mode
POR Reset: A POR circuit holds the device in
Reset when the power supply is turned on. The
POR circuit is active until V
threshold and the delay T
BOR Reset: The on-chip voltage regulator has
a BOR circuit that keeps the device in Reset
until V
delay T
ensures that the voltage regulator output
becomes stable.
2:
3:
System Reset
DD
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
BOR
LOCK
crosses the V
bits
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= PLL lock time (1.5 ms nominal), if PLL is enabled.
has elapsed. The delay T
= Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
in
Startup Delay
Oscillator
the
BOR
T
T
T
T
T
T
T
T
POR
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
DD
—
—
OST
threshold and the
Oscillator
crosses the V
has elapsed.
= 32 ms for a 32 kHz crystal.
Control
Oscillator Startup
POR
BOR
Preliminary
Timer
T
T
T
T
T
OST
OST
OST
OST
OST
—
—
—
—
—
3.
4.
5.
6.
PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
for a specific period of time (T
BOR. The delay T
power supplies have stabilized at the appropri-
ate level for full-speed operation. After the delay
T
inactive; which enables the selected oscillator to
start generating clock cycles.
Oscillator Delay: The total delay for the clock to
be ready for various clock source selections is
given in Table 6-1. Refer to Section 8.0
“Oscillator
information.
When the oscillator clock is ready, the processor
begins execution from location 0x000000. The
user application programs a GOTO instruction at
the Reset address, which redirects program
execution to the appropriate start-up routine.
The Fail-safe clock monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay T
elapsed.
PWRT
PLL Lock Time
has elapsed, the SYSRST becomes
T
T
T
T
LOCK
LOCK
LOCK
LOCK
—
—
—
—
—
—
Configuration”
PWRT
© 2009 Microchip Technology Inc.
ensures that the system
T
T
OSCD
OSCD
OST
T
T
T
T
OSCD
Total Delay
= 102.4 μs for a
OSCD
OSCD
OSCD
PWRT
+ T
+ T
T
T
T
OSCD
OSCD
for
LOCK
OST
OST
—
+ T
+ T
+ T
+ T
) after a
LOCK
OST
OST
+ T
+ T
OST
more
FSCM
LOCK
LOCK
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