DSPIC33FJ12MC202-I/SP Microchip Technology, DSPIC33FJ12MC202-I/SP Datasheet - Page 39
![IC DSPIC MCU/DSP 12K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ12MC202-I/SP
Manufacturer Part Number
DSPIC33FJ12MC202-I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- DSPIC33FJ12MC202-IML PDF datasheet #4
- Current page: 39 of 288
- Download datasheet (5Mb)
TABLE 4-10:
TABLE 4-11:
TABLE 4-12:
P2TCON
P2TMR
P2TPER
P2SECMP
PWM2CON1 05C8
PWM2CON2 05CA
P2DTCON1
P2DTCON2
P2FLTACON 05D0
P2OVDCON
P2DC1
Legend:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
QEI1CON
DFLT1CON
POS1CNT
MAX1CNT
Legend:
SFR Name
SFR Name
Name
SFR
u = uninitialized bit, — = unimplemented, read as ‘0’
u = uninitialized bit, — = unimplemented, read as ‘0’
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr.
01E0 CNTERR
01E2
01E4
01E6
Addr.
05CC
05CE
Addr
020A
020C
05C0
05C2
05C4
05C6 SEVTDIR
05D4
05D6
SFR
0200
0202
0204
0206
0208
2-OUTPUT PWM2 REGISTER MAP
QEI1 REGISTER MAP
I2C1 REGISTER MAP
ACKSTAT
Bit 15
PTDIR
Bit 15
PTEN
Bit 15
I2CEN
DTBPS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
Bit 14
Bit 14
TRSTAT
—
—
Bit 14
—
—
—
—
—
—
—
—
—
—
—
—
QEISIDL
PTSIDL
Bit 13
Bit 13
—
I2CSIDL
—
—
—
—
—
Bit 13
—
—
—
—
—
—
Bit 12 Bit 11 Bit 10
INDX UPDN
Bit 12
—
—
—
—
—
—
—
SCLREL
Bit 12
—
—
—
—
—
—
—
Bit 11
—
—
—
—
—
DTB<5:0>
IPMIEN
Bit 11
—
—
—
—
—
—
IMV<1:0>
Bit 10
QEIM<2:0>
SEVOPS<3:0>
—
—
—
—
—
Bit 9
Bit 10
A10M
BCL
—
—
—
—
—
FAOV1H FAOV1L
POVD1H POVD1L
Bit 9
CEID
Bit 8
—
—
—
PWM Duty Cycle 1 Register
PWM Special Event Compare Register
Maximum Count<15:0>
Position Counter<15:0>
GCSTAT
PWM Timer Count Value Register
DISSLW
PWM Time Base Period Register
Bit 9
SWPAB PCDOUT
QEOUT
PMOD1
—
—
—
Bit 7
Bit 8
—
—
ADD10
SMEN
Bit 8
FLTAM
—
—
Bit 7
Bit 6
DTAPS<1:0>
—
—
—
—
IWCOL
QECK<2:0>
GCEN
Bit 7
TQGATE
Bit 6
PTOPS<3:0>
—
—
—
—
—
Bit 5
STREN
I2COV
Bit 6
Bit 5
—
—
—
—
—
Bit 4
TQCKPS<1:0>
Address Mask Register
PEN1H
Bit 4
ACKDT
Baud Rate Generator Register
Address Register
Bit 5
—
—
—
—
D_A
Bit 3
—
Bit 3
PTCKPS<1:0>
—
—
—
—
—
ACKEN
Transmit Register
Bit 4
Receive Register
DTA<5:0>
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
P
Bit 2
—
Bit 2
IUE
—
—
—
—
RCEN
Bit 3
S
Bit 1
—
POUT1H POUT1L 1111 1111 0000 0000
OSYNC
DTS1A
Bit 1
PTMOD<1:0>
—
—
Bit 2
R_W
PEN
Bit 0
—
PEN1L 0000 0000 1111 1111
FAEN1 0000 0000 0000 0000
DTS1I
UDIS
Bit 0
RSEN
Bit 1
RBF
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Reset State
Reset State
Bit 0
SEN
TBF
Resets
0000
00FF
0000
1000
0000
0000
0000
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