ATMEGA644PA-AUR Atmel, ATMEGA644PA-AUR Datasheet - Page 19
![IC MCU AVR 64K FLASH 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA644PA-AUR
Manufacturer Part Number
ATMEGA644PA-AUR
Description
IC MCU AVR 64K FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PA-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA644PA-AUR
Manufacturer:
ATMEL
Quantity:
1 400
Part Number:
ATMEGA644PA-AUR
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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7. AVR Memories
7.1
7.2
8272A–AVR–01/10
Overview
In-System Reprogrammable Flash Program Memory
T h i s s e c t i o n d e s c r i b e s t h e d i f f e r e n t m e m o r i e s i n t h e
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an EEPROM Memory for
data storage. All three memory spaces are linear and regular.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains 16/32/64/128K bytes
On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instruc-
tions are 16 or 32 bits wide, the Flash is organized as 32/64 x 16. For software security, the
Flash Program memory space is divided into two sections, Boot Program section and Applica-
tion Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Program Counter (PC) is 15/16
bits wide, thus addressing the 32/64K program memory locations. The operation of Boot Pro-
gram section and associated Boot Lock bits for software protection are described in detail in
”Memory Programming” on page
description on Flash data serial downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description.
Timing diagrams for instruction fetch and execution are presented in
ing” on page
164A/164PA/324A/324PA/644A/644PA/1284/1284P
15.
295.
”Memory Programming” on page 295
”Instruction Execution Tim-
contains a detailed
19
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