ATMEGA1284-AU Atmel, ATMEGA1284-AU Datasheet - Page 235
ATMEGA1284-AU
Manufacturer Part Number
ATMEGA1284-AU
Description
IC MCU AVR 128K FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1284-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284-AU
Manufacturer:
ATMEL
Quantity:
1 200
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20.9.3
20.9.4
8272A–AVR–01/10
TWSR – TWI Status Register
TWDR – TWI Data Register
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-
vated for as long as the TWINT Flag is high.
• Bits 7:3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status
codes are described
contains both the 5-bit status value and the 2-bit prescaler value. The application designer
should mask the prescaler bits to zero when checking the Status bits. This makes status check-
ing independent of prescaler setting. This approach is used in this datasheet, unless otherwise
noted.
• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 1:0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 20-7.
To calculate bit rates, see
used in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0xB9)
Read/Write
Initial Value
Bit
(0xBB)
Read/Write
Initial Value
TWPS1
0
0
1
1
TWI Bit Rate Prescaler
TWS7
TWD7
R/W
R
7
1
7
1
”Transmission Modes” on page
TWS6
TWD6
R/W
R
TWPS0
0
1
0
1
6
1
6
1
”Bit Rate Generator Unit” on page
TWS5
TWD5
R/W
R
5
1
5
1
TWS4
TWD4
R/W
R
4
1
4
1
Prescaler Value
1
4
16
64
TWD3
TWS3
R/W
R
3
1
219. Note that the value read from TWSR
3
1
TWD2
R/W
R
2
–
0
2
1
214. The value of TWPS1..0 is
TWPS1
TWD1
R/W
R/W
1
0
1
1
TWPS0
TWD0
R/W
R/W
0
0
0
1
TWSR
TWDR
235
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