PIC18F46J11-I/PT Microchip Technology, PIC18F46J11-I/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F46J11-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J11-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2XJXX/4XJXX FAMILY
3.1.2
It is possible to erase one row (1024 bytes of data),
provided
erase/write-protected. Rows are located at static
boundaries beginning at program memory address
000000h, extending to the internal program memory
limit (see Section 2.2 “Memory Maps”).
The Row Erase duration is externally timed and is
controlled by PGC. After the WR bit in EECON1 is set,
a NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by parameter P10 to allow high-voltage
discharge of the memory array.
The
PIC18F2XJXX/4XJXX family device is shown in
Table 3-2. The flowchart shown in Figure 3-3 depicts the
TABLE 3-2:
DS39687D-page 10
Step 1: Enable memory writes.
Step 2: Point to first row in code memory.
Step 3: Enable erase and erase single row.
Step 4: Repeat step 3, with Address Pointer incremented by 1024, until all rows are erased.
Command
0000
0000
0000
0000
0000
0000
0000
4-Bit
code
the
ICSP™ ROW ERASE
sequence
block
84 A6
6A F8
6A F7
6A F6
88 A6
82 A6
00 00
ERASE CODE MEMORY CODE SEQUENCE
Data Payload
is
not
to
code-protected
Row
BSF
CLRF
CLRF
CLRF
BSF
BSF
NOP – hold PGC high for time P9 and low for time P10.
Erase
EECON1, WREN
TBLPTRU
TBLPTRH
TBLPTRL
EECON1, FREE
EECON1, WR
or
a
logic
PIC18F2XJXX/4XJXX
diagram that details the “Start Programming” command
and parameters P9 and P10 is shown in Figure 3-5.
Note 1: If the last row of program memory is
Core Instruction
necessary
2: The TBLPTR register can point at any
3: If code protection has been enabled,
erased, bit 3 of CONFIG1H must also be
programmed as ‘0’.
byte within the row intended for erase.
ICSP Bulk Erase (all program memory
erased) operations can be used to dis-
able code protection. ICSP Row Erase
operations cannot be used to disable
code protection.
to
© 2008 Microchip Technology Inc.
family
completely
device.
The
erase
timing
a