ATMEGA169PV-8AUR Atmel, ATMEGA169PV-8AUR Datasheet - Page 128
ATMEGA169PV-8AUR
Manufacturer Part Number
ATMEGA169PV-8AUR
Description
MCU AVR 16KB FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA169PV-8AU.pdf
(395 pages)
Specifications of ATMEGA169PV-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
54
Interface Type
SPI/USART/USI
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.11 16-bit Timer/Counter Register Description
15.11.1
8018P–AVR–08/10
TCCR1A – Timer/Counter1 Control Register A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Unit B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting.
WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 15-1.
Table 15-2
PWM mode.
Table 15-2.
Note:
Bit
(0x80)
Read/Write
Initial Value
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at TOP.
Mode” on page 120.
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast
COM1A1
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
R/W
7
0
COM1A0
COM1A0/COM1B0
COM1A0/COM1B0
R/W
6
0
for more details.
0
1
0
1
0
1
0
1
COM1B1
R/W
Table 15-1
5
0
COM1B0
R/W
4
0
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to
high level).
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at BOTTOM (non-inverting mode)
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at BOTTOM (inverting mode)
Description
Description
shows the COM1x1:0 bit functionality when the
(1)
R
3
–
0
R
2
–
0
WGM11
ATmega169P
R/W
1
0
WGM10
See ”Fast PWM
R/W
0
0
TCCR1A
128
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