AT32UC3L032-AUR Atmel, AT32UC3L032-AUR Datasheet - Page 65

• Manufacturer Part Number: AT32UC3L032-AUR
• Description: IC MCU AVR32 32K FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-AUR

• Package / Case: 48-TQFP, 48-VQFP
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.98 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 36
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.2.15
10.2.16
10.2.17
32099AS–AVR32–06/09
USART
TC
CAT
3. VERSION register reads 0x200
4. CONFW.WEVSRC and CONFW.WEVEN are not correctly described in the user
1. The RTS output does not function correctly in hardware handshaking mode
1. When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
1. Switch off discharge current when reaching 0V
2. CAT external capacitors are not clamped to ground when CAT is idle
3. CAT DISHIFT field is stuck at zero
4. CAT ACCTRL bit is stuck at zero
The VERSION register reads 0x200 instead of 0x212.
Fix/Workaround
None.
interface
CONFW.WEVSRC is only two bits instead of three bits wide. Only values 0, 1, and 2 can be
written to this register. CONFW.WEVEN is in bit position 10 instead of 11.
Fix/workaround
Only write values 0, 1, and 2 to CONFW.WEVSRC. When reading CONFW.WEVSRC, dis-
regard the third bit. Read/write bit 10 to access CONFW.WEVEN.
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/workaround
None.
The discharge current will switch off when reaching MGCFG1.MAX, not when reaching 0V.
Fix/workaround
None.
The CAT module does not clamp the external capacitors to ground when it is idle. The
capacitors are left floating, so they could accumulate small amounts of charge.
Fix/workaround
None.
The DISHIFT field in the MGCFG1, TGACFG1, TGBCFG1, and ATCFG1 registers is stuck
at zero and cannot be written to a different value. Capacitor discharge time will be deter-
mined only by the DILEN field.
Fix/workaround
None.
AT32UC3L
65