AT32UC3L032-AUR Atmel, AT32UC3L032-AUR Datasheet - Page 57

• Manufacturer Part Number: AT32UC3L032-AUR
• Description: IC MCU AVR32 32K FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-AUR

• Package / Case: 48-TQFP, 48-VQFP
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.98 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 50MHz
• Number Of I /o: 36
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10. Errata
10.1
10.1.1
10.1.2
10.2
10.2.1
32099AS–AVR32–06/09
Rev. C
Rev. B
SCIF
SPI
Processor and Architecture
1. A reset from Supply Monitor 33 will be registered as POR
1. SPI disable does not work in SLAVE mode
2. SPI Bad Serial Clock Generation on 2nd chip select when SCBR = 1, CPOL=1, and
3. SPI data transfer hangs with CSAAT=1 in CSR0 and MODFDIS=0 in MR
4. Disabling SPI has no effect on the TDRE flag
1. RETS behaves incorrectly when MPU is enabled
A Supply Monitor 33 reset will not be detected in the Reset Cause register (RCAUSE) as
BOD33, it will be detected as a Power-on Reset (POR).
Fix/Workaround
None.
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a Software Reset.
NCPHA=0
When multiple CS are in use, if one of the baudrates equals 1 and one of the others does
not equal 1, and CPOL=1 and CPHA=0, an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CPOL=1 and CPHA=0.
When CSAAT=1 in CSR0 and mode fault detection is enabled (MODFDIS=0 in MR), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MODFDIS in MR.
Disabling SPI has no effect on TDRE whereas the write data command is filtered when SPI
is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset
the TDRE flag by writing in the TDR. So if the SPI is disabled during a PDCA transfer, the
PDCA will continue to write data in the TDR (as TDRE stays high) until its buffer is empty,
and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, 2 NOP (minimum), disable SPI. When you want to continue the transfer:
Enable SPI, enable PDCA.
RETS behaves incorrectly when MPU is enabled and MPU is configured so that system
stack is not readable in unprivileged mode.
Fix/Workaround
Make system stack readable in unprivileged mode, or return from supervisor mode using
rete instead of rets. This requires:
1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the
mode bits to the desired value must be done using a single mtsr instruction so it is done
AT32UC3L
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