ATMEGA162-16AUR Atmel, ATMEGA162-16AUR Datasheet - Page 190

MCU AVR 16KB FLASH 16MHZ 44TQFP

ATMEGA162-16AUR

Manufacturer Part Number
ATMEGA162-16AUR
Description
MCU AVR 16KB FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA162-16AUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA162-16AUR
Manufacturer:
Atmel
Quantity:
10 000
USART Baud Rate
Registers – UBRRL
and UBRRH
190
ATmega162/V
(1)
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-
acter Size) in a frame the receiver and transmitter use.
Table 76. UCSZ Bits Settings
• Bit 0 – UCPOL: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOL bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 77. UCPOL Bit Settings
Note:
• Bit 15 – URSEL: Register Select
This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when
reading UBRRH. The URSEL must be zero when writing the UBRRH.
• Bit 14:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
Bit
Read/Write
Initial Value
UCPOL
0
1
UCSZ2
1. The UBRRH Register shares the same I/O location as the UCSRC Register. See the
0
0
0
0
1
1
1
1
Transmitted Data Changed
(Output of TxD Pin)
Rising XCK Edge
Falling XCK Edge
ing UBRRH/ UCSRC Registers” on page 184
register.
URSEL
R/W
R/W
15
7
0
0
R/W
14
UCSZ1
R
6
0
0
0
0
1
1
0
0
1
1
R/W
13
R
5
0
0
R/W
12
R
4
0
0
UBRR[7:0]
UCSZ0
0
1
0
1
0
1
0
1
R/W
R/W
11
3
0
0
Received Data Sampled
(Input on RxD Pin)
Falling XCK Edge
Rising XCK Edge
section which describes how to access this
R/W
R/W
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
10
2
0
0
UBRR[11:8]
R/W
R/W
9
1
0
0
R/W
R/W
8
0
0
0
UBRRH
UBRRL
2513K–AVR–07/09
“Access-

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