PIC16F83-04/P Microchip Technology, PIC16F83-04/P Datasheet - Page 307

• Manufacturer Part Number: PIC16F83-04/P
• Description: IC MCU FLASH 512X14 EE 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F83-04/P

• Core Size: 8-Bit
• Program Memory Size: 896B (512 x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 36Byte
• Cpu Speed: 4MHz
• No. Of: RoHS Compliant
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 36 B
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Data Rom Size: 64 B
• Height: 3.3 mm
• Length: 22.86 mm
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

17.4.8
1997 Microchip Technology Inc.
Baud Rate Generator
In I
register
stops until another reload has taken place. In I
cally. If Clock Arbitration is taking place for instance, the BRG will be reloaded when the SCL pin
is sampled high
Figure 17-18: Baud Rate Generator Block Diagram
Figure 17-19: Baud Rate Generator Timing With Clock Arbitration
2
SDA
SCL
BRG
value
BRG
reload
C master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD
(Figure
SSPM3:SSPM0
17-18). When the BRG is loaded with this value, the BRG counts down to 0 and
(Figure
BRG counts
down
03h
SCL
17-19).
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
SSPM3:SSPM0
Preliminary
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG counts
down
Reload
Control
CLKOUT
01h
2
C master mode, the BRG is reloaded automati-
Reload
Section 17. MSSP
BRG counts
down
00h (hold off)
BRG Down Counter
DX-1
SSPADD<6:0>
SCL allowed to transition high
03h
DS31017A-page 17-31
Fosc/4
02h
17