AT32UC3L032-ZAUT Atmel, AT32UC3L032-ZAUT Datasheet - Page 831
AT32UC3L032-ZAUT
Manufacturer Part Number
AT32UC3L032-ZAUT
Description
IC MCU AVR32 32KB FLASH 48VQFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3L-EK.pdf
(858 pages)
Specifications of AT32UC3L032-ZAUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 831 of 858
- Download datasheet (13Mb)
35.4.2
35.4.3
32099F–11/2010
FLASHCDW
HMATRIX
3. RETS behaves incorrectly when MPU is enabled
1. Flash selfprogramming may fail in one wait state mode
2. Chip Erase
3. Fuse Programming
4. Wait 500ns before reading from the flash after switching read mode
5. VERSION register reads 0x100
1. In the PRAS and PRBS registers, the MxPR fields are only two bits
RETS behaves incorrectly when MPU is enabled and MPU is configured so that system
stack is not readable in unprivileged mode.
Fix/Workaround
Make system stack readable in unprivileged mode, or return from supervisor mode using
rete instead of rets. This requires:
1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the
mode bits to the desired value must be done using a single mtsr instruction so it is done
atomically. Even if this step is described in general as not safe in the UC technical reference
manual, it is safe in this very specific case.
2. Execute the RETE instruction.
Writes in flash and user pages may fail if executing code located in the address space
mapped to the flash and if the flash controller is configured in one wait state mode (the Flash
Wait State bit in the Flash Control Register (FCR.FWS) is 1).
Fix/Workaround
Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0).
Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst
length transfer mode (MCFG1.ULBT=0) and the HMATRIX slave 0 (FLASHCDW) to use the
maximum slot cycle limit (SCFG0.SLOT_CYCLE=255).
When performing a chip erase, the device may report that it is protected (IR=0x11) and that
chip erase failed, even if the chip erase was successful.
Fix/Workaround
Perform a reset before any further read and programming.
Programming of fuses does not work.
Fix/Workaround
Do not program fuses. All fuses will be erased during chip erase command.
After switching between normal read mode and high-speed read mode, the application must
wait at least 500ns before attempting any access to the flash.
Fix/Workaround
Solution 1: Make sure that the appropriate instructions are executed from RAM, and that a
waiting-loop is executed from RAM waiting 500ns or more before executing from flash.
Solution 2: Execute from flash with a clock with period longer than 500ns. This guarantees
that no new read access is attempted before the flash has had time to settle in the new read
mode.
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
AT32UC3L016/32/64
831
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