AT32UC3L032-ZAUT Atmel, AT32UC3L032-ZAUT Datasheet - Page 362

• Manufacturer Part Number: AT32UC3L032-ZAUT
• Description: IC MCU AVR32 32KB FLASH 48VQFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-ZAUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.6.1
Figure 19-2. Baud Rate Generator
19.6.1.1
32099F–11/2010
Baud Rate Generator
CLK_USART/DIV
CLK
CLK_USART
Baud Rate in Asynchronous Mode
Reserved
USCLKS
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (MR) between:
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field
of the Baud Rate Generator Register (BRGR). If CD is programmed at 0, the Baud Rate Gener-
ator does not generate any clock. If CD is programmed at 1, the divider is bypassed and
becomes inactive.
If the external CLK clock is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be longer than a CLK_USART period. The frequency of the signal
provided on CLK must be at least 4.5 times lower than CLK_USART.
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (BRGR). The
resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is
the highest possible clock and that OVER is programmed at 1.
0
1
3
2
• CLK_USART
• a division of CLK_USART, the divider being product dependent, but generally set to 8
• the external clock, available on the CLK pin
Baudrate
16-bit Counter
=
--------------------------------------------
(
CD
8 2 Over
SelectedClock
(
–
USCLKS= 3
)CD
0
SYNC
)
CD
>1
0
1
0
1
OVER
Sampling
Divider
AT32UC3L016/32/64
FIDI
0
1
SYNC
CLK
BaudRate
Sampling
Clock
Clock
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