ATTINY85-15ST1 Atmel, ATTINY85-15ST1 Datasheet - Page 60
![MCU AVR 8K FLASH 15MHZ 8-SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY85-15ST1
Manufacturer Part Number
ATTINY85-15ST1
Description
MCU AVR 8K FLASH 15MHZ 8-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-15MZ.pdf
(196 pages)
Specifications of ATTINY85-15ST1
Package / Case
8-SOIC (3.9mm Width)
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Speed
16MHz
Number Of I /o
6
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
512 x 8
Program Memory Size
8KB (8K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.3
11.4
60
General Interrupt Flag Register – GIFR
Pin Change Mask Register – PCMSK
ATtiny25/45/85
• Bits 7, 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bits 5..0 – PCINT5..0: Pin Change Enable Mask 5..0
Each PCINT5..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT5..0 is cleared, pin change interrupt on the corresponding I/O pin
is disabled.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
R
7
–
0
7
–
0
INTF0
R/W
R
6
–
0
6
0
PCINT5
PCIF
R/W
R/W
5
1
5
0
PCINT4
R/W
R
4
1
4
–
0
PCINT3
R/W
R
3
1
3
–
0
PCINT2
R/W
2
1
R
2
–
0
PCINT1
R/W
1
1
R
1
–
0
PCINT0
R/W
0
1
R
0
–
0
7598H–AVR–07/09
PCMSK
GIFR
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