ATTINY85-15ST1 Atmel, ATTINY85-15ST1 Datasheet - Page 125

• Manufacturer Part Number: ATTINY85-15ST1
• Description: MCU AVR 8K FLASH 15MHZ 8-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY85-15ST1

• Package / Case: 8-SOIC (3.9mm Width)
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Speed: 16MHz
• Number Of I /o: 6
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7598H–AVR–07/09
The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is
written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the nor-
mal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as
a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to
this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC
Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on
ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions
are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
Table 18-5.
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections
ADPS1
0
0
1
1
0
0
1
1
ADPS0
0
1
0
1
0
1
0
1
ATtiny25/45/85
Division Factor
128
16
32
64
2
2
4
8
125