ATMEGA165PV-8MUR Atmel, ATMEGA165PV-8MUR Datasheet - Page 47
ATMEGA165PV-8MUR
Manufacturer Part Number
ATMEGA165PV-8MUR
Description
MCU AVR 16KB FLASH 8MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165PV-8MUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.3
9.3.1
9.4
8019K–AVR–11/10
Internal Voltage Reference
Watchdog Timer
Voltage Reference Enable Signals and Start-up Time
ATmega165P features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega165P resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 48
details.
Table 9-1.
WDTON
Unprogrammed
Programmed
ACBG bit in ACSR).
Table 9-2 on page
WDT Configuration as a Function of the Fuse Settings of WDTON
CC
Safety
Level
= 5V. See characterization data for typical values at other V
1
2
“System and Reset Characteristics” on page
51. The WDR – Watchdog Reset – instruction resets the Watchdog
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
Table 9-2 on page
ATmega165P
302. To save power, the
How to Change Time-
out
Timed sequence
Timed sequence
Table
9-1. Refer to
CC
51.
levels. By
for
47
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