AT90PWM316-16SU Atmel, AT90PWM316-16SU Datasheet - Page 43

• Manufacturer Part Number: AT90PWM316-16SU
• Description: MCU AVR 16K ISP FLSH 16MHZ32SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM316-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 32SOIC
• Device Core: AVR
• Family Name: 90P
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
7710E–AVR–08/10
Brown-out Detector
Internal Voltage Reference
Watchdog Timer
Port Pins
On-chip Debug System
the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up
to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all
sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep
mode. Refer to
Comparator.
If the Brown-out Detector is not needed by the application, this module should be turned off. If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-
nificantly to the total current consumption. Refer to
on how to configure the Brown-out Detector.
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to
age Reference” on page 49
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
input buffer is enabled and the input signal is left floating or have an analog signal level close to
V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to “Digital Input Disable Register 1– DIDR1” and “Digital Input Disable Register 0
– DIDR0” on
If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the
main clock source is enabled, and hence, always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
CC
/2, the input buffer will use excessive power.
page 234
“Watchdog Timer” on page 50
CC
“Analog Comparator” on page 229
I/O
/2 on an input pin can cause significant current even in active mode. Digital
) and the ADC clock (clk
and
page 253
for details on the start-up time.
“I/O-Ports” on page 60
for details.
ADC
for details on how to configure the Watchdog Timer.
) are stopped, the input buffers of the device will
“Brown-out Detection” on page 47
for details on how to configure the Analog
for details on which pins are enabled. If the
AT90PWM216/316
“Internal Volt-
for details
43