PIC16F87-E/SS Microchip Technology, PIC16F87-E/SS Datasheet - Page 153
![IC MCU FLASH 4KX14 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F87-E/SS
Manufacturer Part Number
PIC16F87-E/SS
Description
IC MCU FLASH 4KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F87-IP.pdf
(228 pages)
5.PIC16F87-IP.pdf
(8 pages)
6.PIC16F87-IP.pdf
(4 pages)
7.PIC16F87-IP.pdf
(8 pages)
8.PIC16F87-IP.pdf
(24 pages)
Specifications of PIC16F87-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F87-IP PDF datasheet #4
- PIC16F87-IP PDF datasheet #5
- PIC16F87-IP PDF datasheet #6
- PIC16F87-IP PDF datasheet #7
- PIC16F87-IP PDF datasheet #8
- Current page: 153 of 688
- Download datasheet (3Mb)
9.9
1997 Microchip Technology Inc.
GPIO and the TRISGP Register
GPIO is an 8-bit I/O register. Only the low order six bits are implemented (GP5:GP0). Bits 7 and
6 are unimplemented and read as ‘0’s. Any GPIO pin (except GP3) can be programmed
individually as input or output. The GP3 pin is an input only pin.
The TRISGP register controls the data direction for GPIO pins. A ‘1’ in a TRISGP register bit
puts the corresponding output driver in a hi-impedance mode. A ‘0’ puts the contents of the
output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which
is input only and its TRIS bit will always read as '1'. Upon reset, the TRISGP register is all ‘1’s,
making all pins inputs.
A read of the GPIO port, reads the pins not the output data latches. Any input must be present
until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain
unchanged until the output latch is rewritten.
Example 9-8: Initializing GPIO
Figure 9-11: Block Diagram of GP5:GP0 Pins
The configuration word can set several I/O’s to alternate functions. When acting as alternate
functions the pins will read as ‘0’ during port read. The GP0, GP1, and GP3 pins can be config-
ured with weak pull-ups and also with interrupt on change. The interrupt on change and weak
pull-up functions are not pin selectable. Interrupt on change is enabled by setting INTCON<3>.
If the device configuration bits select one of the external oscillator modes, the GP4 and GP5 pin’s
GPIO functions are overridden and these pins are used for the oscillator.
CLRF
CLRF
BSF
MOVLW
MOVWF
Note 1: I/O pins have protection diodes to V
GP3 is input only with no data latch and no output drivers.
STATUS
GPIO
STATUS, RP0
0xCF
TRISGP
Data
Bus
WR
Port
W
Reg
TRIS ‘f’
; Bank0
; Initialize GPIO by clearing output
;
; Select Bank1
; Value used to initialize data direction
; GP<3:0> = inputs GP<5:4> = outputs
;
D
D
CK
CK
Reset
TRIS
Latch
Data
Latch
data latches
TRISGP<7:6> always read as '0'
Q
Q
Q
Q
RD Port
Section 9. I/O Ports
DD
and V
SS
.
V
V
P
N
SS
DD
I/O
pin
(1)
DS31009A-page 9-13
9
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