DSPIC30F2010T-20E/SOG Microchip Technology, DSPIC30F2010T-20E/SOG Datasheet
DSPIC30F2010T-20E/SOG
Specifications of DSPIC30F2010T-20E/SOG
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DSPIC30F2010T-20E/SOG Summary of contents
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... Decimal Adjust Instruction The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>). © 2008 Microchip Technology Inc. dsPIC30F2010 4. PSV Operations Using SR In certain instructions, fetching one of the operands from program memory using Program Space Visibility (PSV) will corrupt specific bits in the STATUS Register, SR ...
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... SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration. The following sections describe the errata and work around to these errata, where they may apply. © 2008 Microchip Technology Inc. ® DSC ...
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... Y data memory is not immediately followed by a DSP MAC type instruction that performs a read operation of a location in Y data memory. © 2008 Microchip Technology Inc. dsPIC30F2010 2. Module: MAC Class Instructions with +4 Address Modification Sequential MAC class instructions, which prefetch data from Y data space using +4 address modification, will cause an address error trap ...
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... Result in W3 (3) SR<1:0> bits , Result in W3 (3) SR<1:0> bits (3) SR<1:0> bits , Result in W4 (3) SR<1:0> bits , Result in W2 (3) SR<1:0> bits (4) SR<15:10> bits CORRECT RESULTS ;Load PSVPAG register ;indirect PSV access ;from 0x000200 ;works ok ;from program memory ;results are ok! © 2008 Microchip Technology Inc. ...
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... Note: For details on the functionality of EDT bit, see section 2.9.2.4 in the dsPIC30F Family Reference Manual. © 2008 Microchip Technology Inc. dsPIC30F2010 6. Module: Interrupting a REPEAT When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap: 1 ...
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... When these events occur, the output compare module will drive the pin low for one instruction cycle (T ) after the module is enabled. CY Work around None. However, the user may use a timer interrupt and write to the associated PORT register to control the pin manually. © 2008 Microchip Technology Inc ...
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... Work around None. If ADC event trigger from the INT0 pin is required, initialize SMPI<3:0> to ‘0000’ (interrupt on every conversion). © 2008 Microchip Technology Inc. dsPIC30F2010 13. Module: Watchdog Timer The Watchdog Timer does not function as specified. If the CLRWDT instruction is not executed ...
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... One may use a large DISI value and then set the DISICNT register to zero, as shown in Example 10. A macro may also be used to perform this task, as shown in Example 11. // protect CPU IPL modification // set CPU IPL remove DISI protection // safely modify the CPU IPL © 2008 Microchip Technology Inc. ...
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... IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2008 Microchip Technology Inc. 18. Module: QEI Interrupt Generation The Quadrature Encoder Interface (QEI) module does not generate an interrupt when MAXCNT is set to 0xFFFF and the following events occur: 1. POSCNT underflows from 0x0000 to 0xFFFF. ...
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... Sleep mode. Example 13 demonstrates the work around described above would apply to a dsPIC30F2010 device. ; Ensure flag is reset ; Return from Interrupt Service Routine the function call would be following the or _GotoSleep © 2008 Microchip Technology Inc. ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2008 Microchip Technology Inc. Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... If the D_A flag and the I2COV flag are both set, a valid data byte was received and a previous valid data byte was lost. It will be necessary to code for handling this overflow condition. © 2008 Microchip Technology Inc slave interrupt 2 C nodes. ...
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... Table 22-17 “AC Characteristics: Internal RC Accuracy” of the “dsPIC30F2010 Data Sheet” (DS70118). The actual internal FRC accuracy is: • ±4% for 25°C • ±5% for -40°C and 85°C • ±6% for 125°C © 2008 Microchip Technology Inc. dsPIC30F2010 2 24. Module there are two I ...
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... C bus, and can cause 2 C module are set to values ‘1’ and 2 C module and the first data 2 C masters should be synchro module to be initialized 2 C module is with other modules that have 2 C module module. © 2008 Microchip Technology Inc. ...
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... Port Pin Multiplexed with IC1), and 24 (FRC). Revision H (5/2008) 2 Added silicon issues 25 and 26 (I C), and 27 (Timer). Revision J (9/2008) 2 Replaced issues 20 and with issue 30 (I Added silicon issues 26 (PLL Lock Status Bit), 27 (PSV 2 Operations) and 28-30 (I C). © 2008 Microchip Technology Inc. Removed 2 C), 22 (Motor 2 C). dsPIC30F2010 DS80186J-page 15 ...
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... NOTES: DS80186J-page 16 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...