DSPIC30F2010T-20E/SOG Microchip Technology, DSPIC30F2010T-20E/SOG Datasheet
DSPIC30F2010T-20E/SOG
Specifications of DSPIC30F2010T-20E/SOG
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DSPIC30F2010T-20E/SOG Summary of contents
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... Microchip Technology Inc. dsPIC30F2010 High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70118J ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Single-cycle Multiply-Accumulate (MAC) operation • 40-stage Barrel Shifter • Dual data fetch © 2011 Microchip Technology Inc. PIC30F2010 ds Peripheral Features: • High current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption Output SRAM EEPROM Timer Input Comp/Std Bytes Bytes 16-bit Cap PWM 512 1024 Motor A/D 10-bit Control 1 Msps PWM Yes © 2011 Microchip Technology Inc. ...
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... OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 (1) 28-Pin QFN-S AN2/SS1/CN4/RB2 AN3/INDX/CN5 RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2011 Microchip Technology Inc. MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 3 26 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS70118J-page 6 to receive the most current information on all of our products. © 2011 Microchip Technology Inc. ...
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... This document contains device specific information for the dsPIC30F2010 device. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance microcontroller (MCU) architecture. Figure 1-1 device block diagram for the dsPIC30F2010 device. © 2011 Microchip Technology Inc. dsPIC30F2010 Manual” 16-bit shows a DS70118J-page 7 ...
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... PORTD 16 16 Output 2 Compare I C™ Module Motor Control UART1 PWM EMUD3/AN0/VREF+/CN2/RB0 EMUC3/AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 PORTB EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 EMUD2/OC2/IC2/INT2/RD1 PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 FLTA/INT0/SCK1/OCFA/RE8 PORTE PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 PORTF © 2011 Microchip Technology Inc. ...
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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2011 Microchip Technology Inc. Description Analog input channels. Positive supply for analog module. This pin must be connected at all times. Ground reference for analog module. This pin must be connected at all times. ...
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... UART1 Alternate Receive. UART1 Alternate Transmit. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. Analog Voltage Reference (High) input. Analog Voltage Reference (Low) input. Analog = Analog input O = Output P = Power 2 C™ © 2011 Microchip Technology Inc. ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2011 Microchip Technology Inc. dsPIC30F2010 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions ...
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... The upper byte of the STATUS register contains the DSP adder/subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. © 2011 Microchip Technology Inc. ...
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... AD39 DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 Program Space Visibility Page Address ...
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... Signed divide: Wm/Wn → W0; Rem → W1 Unsigned divide: Wm/Wn → W0; Rem → W1 operations, which Table 3-3. DSP INSTRUCTION SUMMARY Algebraic ACC WB? Operation Yes – – Yes • change in A Yes • – x • – x • y Yes © 2011 Microchip Technology Inc. ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2011 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array dsPIC30F2010 Round u r Logic Zero Backfill DS70118J-page 15 ...
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... OVBTE) in the INTCON1 register (refer to rupts”) is set. This allows the user to take immediate action, for example, to correct system gain. Section 5.0 “Inter- © 2011 Microchip Technology Inc. ...
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... No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2011 Microchip Technology Inc. dsPIC30F2010 2.4.2.2 Accumulator ‘Write-Back’ The MAC class of instructions (with the exception of MPY, MPY ...
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... The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. © 2011 Microchip Technology Inc. ...
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... Configuration bits. Otherwise, bit 23 is always clear. Note: The address map shown in conceptual, and the actual memory con- figuration may vary across individual devices depending on available memory. © 2011 Microchip Technology Inc. FIGURE 3-1: Manual” Figure 3-1 is dsPIC30F2010 PROGRAM SPACE MEMORY ...
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... Note: Program Space Visibility cannot be used to access bits <23:16> word in program memory. DS70118J-page 20 Program Space Address Access Space <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> 0 PSVPAG<7:0> 23 bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA <15:0> Data EA <15:0> Data EA <14:0> 0 Byte Select © 2011 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’) © 2011 Microchip Technology Inc. dsPIC30F2010 A set of Table Instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the least significant word of the program address ...
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... Execution in the last iteration - Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle © 2011 Microchip Technology Inc. ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2011 Microchip Technology Inc. dsPIC30F2010 Program Space 0x0000 (1) PSVPAG ...
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... Unimplemented SFR or SRAM locations read as ‘0’. DS70118J-page 24 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 256 bytes 0x08FE 0x0900 Y Data RAM (Y) 256 bytes 0x0A00 (See Note) 0x8000 X Data Unimplemented (X) 0xFFFE LSB 2560 bytes Near Data Space © 2011 Microchip Technology Inc. ...
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... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS SFR Space (Y Space) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2011 Microchip Technology Inc. dsPIC30F2010 SFR Space Unused Y Space Unused Unused MAC Class Ops Read-Only ...
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... FIGURE 3-8: MSB 15 0x0000 0001 Byte 1 0x0000 Byte 3 0003 0x0000 Byte 5 0005 ® Post-Modified Register Indirect DATA ALIGNMENT LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2011 Microchip Technology Inc. ...
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... Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2011 Microchip Technology Inc. dsPIC30F2010 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70118J-page 30 © 2011 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset Register Indirect with Literal Offset © 2011 Microchip Technology Inc. 4.1 Instruction Addressing Modes The Addressing modes in the Addressing modes optimized to support the specific features of individual instructions. The Addressing ...
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... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode source and itself. Certain operations, such as NOP, do not have any operands. © 2011 Microchip Technology Inc. ...
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... Bidirectional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries). © 2011 Microchip Technology Inc. dsPIC30F2010 4.2.1 START AND END ADDRESS The Modulo Addressing scheme requires that a ...
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... W0,MODCON ;enable W1, X AGU for modulo MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x1110,W1 ;point W1 to buffer DO AGAIN,#0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0,W0 ;increment the fill value © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. If the length of a bit-reversed buffer then the last ‘N’ bits of the data buffer start address must be zeros. XB<14:0> is the bit-reversed address modifier or ‘pivot point’ ...
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... Modifier values greater than 256 words exceed the data memory available on the dsPIC30F2010 device. DS70118J-page 36 Decimal XB<14:0> Bit-Reversed Address Modifier Value Bit-Reversed Address A0 Decimal (1) 0x4000 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 © 2011 Microchip Technology Inc. ...
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... The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. © 2011 Microchip Technology Inc. dsPIC30F2010 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit ...
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... INT3 – External Interrupt Reserved 38 46 Reserved 39 47 PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA – PWM Fault Reserved 45-53 53-61 Reserved Lowest Natural Order Priority © 2011 Microchip Technology Inc. ...
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... A momentary dip in the power supply to the device has been detected, which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2011 Microchip Technology Inc. dsPIC30F2010 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere ...
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... Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector © 2011 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 0x00007E 0x000080 0x000082 0x000084 0x000094 0x0000FE ...
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... The RETFIE (Return from Interrupt) instruction will unstack the program counter and status registers to return the processor to its state prior to the interrupt sequence. © 2011 Microchip Technology Inc. 5.5 Alternate Vector Table In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Using Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. dsPIC30F2010 Master Clear (MCLR). This allows customers to manu- facture boards with unprogrammed devices, and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed ...
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... NVMKEY register. Refer to DD “Programming Operations” Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2011 Microchip Technology Inc. Section 6.6 for further details. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2011 Microchip Technology Inc. dsPIC30F2010 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2011 Microchip Technology Inc. ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70118J-page 48 © 2011 Microchip Technology Inc. ...
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... The write typically requires complete, but the write time will vary with voltage and temperature. © 2011 Microchip Technology Inc. A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- sible for waiting for the appropriate duration of time before initiating another data EEPROM write/erase operation ...
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... Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2011 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2011 Microchip Technology Inc. dsPIC30F2010 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. © 2011 Microchip Technology Inc. ...
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... WR Port Data Latch Read LAT Read Port © 2011 Microchip Technology Inc output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx), read the latch. ...
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... This module is capable of ) will be detecting input change-of-states even in Sleep mode, OL when the clocks are disabled. There are exter- nal signals (CN0 through CN21) that may be selected (enabled) for generating an interrupt request on a change-of-state. © 2011 Microchip Technology Inc. ...
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TABLE 8-1: dsPIC30F2010 PORT REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CA — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 ...
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... NOTES: DS70118J-page 56 © 2011 Microchip Technology Inc. ...
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... Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit period register match or falling edge of external gate signal © 2011 Microchip Technology Inc. dsPIC30F2010 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. presents a block diagram of the 16-bit timer module. ...
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... Reset to 0x0000. When a match between the timer and the period regis- ter occurs, an interrupt can be generated, if the respective timer interrupt enable bit is asserted. TCKPS<1:0> TSYNC Sync 1 (3) 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2011 Microchip Technology Inc. ...
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... XTAL SOSCO pF 100K © 2011 Microchip Technology Inc. dsPIC30F2010 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the period register, and is then Reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer ...
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... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2011 Microchip Technology Inc. For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer. ...
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... Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70118J-page 62 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 X Gate 0 1 Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2011 Microchip Technology Inc. ...
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... Event Flag 1 TGATE See NOTE Note: The dsPIC30F2010 does not have an external pin input to TIMER3. The following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2011 Microchip Technology Inc. dsPIC30F2010 PR2 TMR2 Q D TGATE Q CK TON ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). © 2011 Microchip Technology Inc. ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70118J-page 66 © 2011 Microchip Technology Inc. ...
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... ICBNE, ICOV ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2011 Microchip Technology Inc. dsPIC30F2010 The key operational features of the Input Capture module are: • Simple Capture Event mode • ...
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... The input capture interrupt flag is set on every edge, rising and falling. • The interrupt on Capture mode setting bits, ICI<1:0>, is ignored, since every capture generates an interrupt. • A capture overflow condition is not generated in this mode. © 2011 Microchip Technology Inc. ...
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... Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. © 2011 Microchip Technology Inc. dsPIC30F2010 11.2.2 INPUT CAPTURE IN CPU IDLE ...
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TABLE 11-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... TMR3<15:0> TMR2<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective Output Compare channels 1and 2. © 2011 Microchip Technology Inc. dsPIC30F2010 The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2011 Microchip Technology Inc. ...
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... The interrupt is enabled via the respective compare inter- rupt enable (OCxIE) bit, located in the corresponding IEC Control register. © 2011 Microchip Technology Inc. 12.5 Output Compare Operation During CPU Sleep Mode When the CPU enters the Sleep mode, all internal clocks are stopped ...
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TABLE 12-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — OCFRZ OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — OCFRZ OCSIDL — Legend: ...
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... Digital Filter Programmable INDX Digital Filter 3 © 2011 Microchip Technology Inc. The Quadrature Encoder Interface (QEI key fea- ture requirement for several motor control applications, such as Switched Reluctance (SR) and AC Induction Motor (ACIM). The operational features of the QEI are, but not limited to: • ...
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... UPDN signal is supplied to a SFR bit UPDN (QEICON<11> read-only bit. Note: QEI pins are multiplexed with analog inputs. User must insure that all QEI asso- ciated pins are set as digital inputs in the ADPCFG register. © 2011 Microchip Technology Inc. ...
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... CY To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2011 Microchip Technology Inc. dsPIC30F2010 13.5 Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode QEIM< ...
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... The QEI interrupt flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 status register. Enabling an interrupt is accomplished via the respec- tive enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register. © 2011 Microchip Technology Inc. ...
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TABLE 13-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB DFLTCON 0124 — — — — — POSCNT 0126 ...
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... NOTES: DS70118J-page 80 © 2011 Microchip Technology Inc. ...
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... I/O pin. A simplified block diagram of the Motor Control PWM modules is shown in Figure 14-1. The PWM module allows several modes of operation which are beneficial for specific power control applications. © 2011 Microchip Technology Inc. dsPIC30F2010 DS70118J-page 81 ...
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... Generator and Override Logic PWM Channel 2 Dead-Time Generator 2 Generator and Override Logic PWM Channel 1 Dead-Time Generator 1 Generator and Override Logic Special Event Postscaler PTDIR PWM3H PWM3L Output PWM2H Driver Block PWM2L PWM1H PWM1L FLTA Special Event Trigger © 2011 Microchip Technology Inc. ...
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... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2011 Microchip Technology Inc. dsPIC30F2010 14.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...
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... COUNT MODE) • • • (PTPER + 1) PTMR Prescale Value PWM CY The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined using Equation 14-3: EQUATION 14-3: PWM RESOLUTION • log ( PWM Resolution = log (2) © 2011 Microchip Technology Inc. using ) CY ...
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... EDGE-ALIGNED PWM New Duty Cycle Latched PTPER PTMR Value 0 Duty Cycle Period © 2011 Microchip Technology Inc. dsPIC30F2010 14.4 Center-Aligned PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Counting mode (see Figure 14-3). ...
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... On a load of the down timer due to a duty cycle comparison edge event. • write to the DTCON1 register. • On any device Reset. Note: The user should not modify the DTCON1 values while the PWM module is operat- ing (PTEN = 1). Unexpected results may occur. © 2011 Microchip Technology Inc. 14-4, the , ...
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... PTPER register occurs, the PTMR reg- ister is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. © 2011 Microchip Technology Inc. dsPIC30F2010 14.10 PWM Output Override The PWM output override bits allow the user to manu- ally drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...
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... The PWM update lockout feature is enabled by setting the UDIS control bit in the PWMCON2 SFR. The UDIS bit affects all duty cycle buffer registers and the PWM time base period buffer, PTPER. No duty cycle changes or period value changes will have effect while UDIS = 1. © 2011 Microchip Technology Inc. ...
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... The special event output postscaler is cleared on the following events: • Any write to the SEVTCMP register • Any device Reset © 2011 Microchip Technology Inc. dsPIC30F2010 14.15 PWM Operation During CPU Sleep Mode The FLTA input pin has the ability to wake the CPU from Sleep mode ...
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TABLE 14-1: PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PWMCON2 01CA — ...
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... SCL transitions while SPI- ROV is ‘1’, effectively disabling the module until SPIx- BUF is read by user software. © 2011 Microchip Technology Inc. dsPIC30F2010 Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) is moved to the receive buffer ...
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... Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Primary Secondary Prescaler Prescaler F CY 1:1, 1:4, 1:1-1:8 1:16, 1:64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2011 Microchip Technology Inc. ...
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... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb, even if SSx had been de-asserted in the middle of a transmit/receive. © 2011 Microchip Technology Inc. dsPIC30F2010 15.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down ...
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TABLE 15-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, read ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 16-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2011 Microchip Technology Inc. 16.1.1 VARIOUS I The following types • Slave operation with 7-bit addressing 2 • Slave operation with 10-bit addressing 2 • ...
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... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2011 Microchip Technology Inc. ...
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... SCL high (see timing diagram). The inter- rupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2011 Microchip Technology Inc. dsPIC30F2010 16.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 98
... C module generates two interrupt flags, MI2CIF Master Interrupt Flag) and SI2CIF (I rupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. © 2011 Microchip Technology Inc Slave Inter- ...
Page 99
... Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released. © 2011 Microchip Technology Inc. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the data direction bit (R_W) is logic ‘ ...
Page 100
... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle bus © 2011 Microchip Technology Inc. ...
Page 101
TABLE 16-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 I2CEN ...
Page 102
... NOTES: DS70118J-page 102 © 2011 Microchip Technology Inc. ...
Page 103
... Internal Data Bus UTXBRK Data UxTX Parity Note only. © 2011 Microchip Technology Inc. 17.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits • ...
Page 104
... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16X Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA Control Signals UxRXIF © 2011 Microchip Technology Inc. ...
Page 105
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2011 Microchip Technology Inc. dsPIC30F2010 17.3 Transmitting Data 17.3.1 ...
Page 106
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2011 Microchip Technology Inc. RXB) ...
Page 107
... The URXISEL control bit does not have any impact on interrupt generation in this mode, since an interrupt (if enabled) will be generated every time the received word has the 9th bit set. © 2011 Microchip Technology Inc. dsPIC30F2010 17.7 Loopback Mode Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX pin ...
Page 108
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2011 Microchip Technology Inc. ...
Page 109
TABLE 17-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG 0212 ...
Page 110
... NOTES: DS70118J-page 110 © 2011 Microchip Technology Inc. ...
Page 111
... AN3 AN3 AN4 AN4 AN5 AN5 AN1 © 2011 Microchip Technology Inc. dsPIC30F2010 The ADC module has six 16-bit registers: • A/D Control Register1 (ADCON1) • A/D Control Register2 (ADCON2) • A/D Control Register3 (ADCON3) • A/D Input Select Register (ADCHS) • ...
Page 112
... The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. interrupts to move the eight © 2011 Microchip Technology Inc. ...
Page 113
... If sequential sampling is specified, the A/D will continue at the next sample pulse which corresponds with the next channel converted. If simultaneous sampling is specified, the A/D will continue with the next multichannel group conversion sequence. © 2011 Microchip Technology Inc. 18.6 Selecting the A/D Conversion Clock The A/D conversion requires 12 T A/D conversion clock is software selected using a 6-bit counter ...
Page 114
... Configuration details that are not critical to the conversion speed have been omitted. Figure 18-2 depicts the recommended circuit for the conversion rates above 500 ksps. FIGURE 18-2: ADC VOLTAGE REFERENCE SCHEMATIC 0.1 μF 0.01 μ dsPIC30F2010 DS70118J-page 114 summarizes μ μF © 2011 Microchip Technology Inc. ...
Page 115
... T AD 500 ksps Up to 256. 300 ksps Note 1: External V - and V + pins must be used for correct operation. See REF REF circuit. © 2011 Microchip Technology Inc. R Max V Temperature S DD 500Ω 4.5V -40°C to +85°C to 5.5V ANx 500Ω 4.5V -40°C to +85° ...
Page 116
... Sequential sampling must be used in this configuration to allow adequate sampling time on each input Table 18-2 + and V - pins following REF REF Figure 18 95. © 2011 Microchip Technology Inc. ...
Page 117
... DAC) HOLD Note: C value depends on device package and is not tested. Effect of C PIN © 2011 Microchip Technology Inc. 18.8 A/D Acquisition Requirements The analog input model of the 10-bit ADC is shown in Figure 18-3. The total sampling time for the A ...
Page 118
... Each of the output formats translates to a 16-bit result on the data bus. Write data will always be in right justified (integer) format. d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 © 2011 Microchip Technology Inc. ...
Page 119
... Analog levels on any pin that is defined as a digital input (including the ANx pins), may cause the input buffer to consume current that exceeds the device specifications. © 2011 Microchip Technology Inc. dsPIC30F2010 18.14 Connection Considerations The analog inputs have diodes to V protection ...
Page 120
TABLE 18-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ...
Page 121
... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2011 Microchip Technology Inc. dsPIC30F2010 19.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 122
... RC Oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70118J-page 122 Description (1) . (2) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2011 Microchip Technology Inc. ...
Page 123
... FIGURE 19-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2011 Microchip Technology Inc. dsPIC30F2010 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer Switching and Control ...
Page 124
... FPR1 FPR0 OSC2 Function CLKO CLKO OSC2 0 0 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 x OSC2 1 x — — See Note 1 and 2 — — See Note 1 and 2 — — See Note 1 and 2 © 2011 Microchip Technology Inc. ...
Page 125
... OSCTUN functionality has been provided to help customers compensate temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2011 Microchip Technology Inc. TABLE 19-4: TUN<3:0> Bits 0111 0110 0101 0100 0011 ...
Page 126
... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write 0x78 to OSCCON high Byte Write 0x9A to OSCCON high Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2011 Microchip Technology Inc. ...
Page 127
... V DD Brown-out Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2011 Microchip Technology Inc. dsPIC30F2010 19.3.1 POR: POWER-ON RESET A power-on event will generate an internal POR pulse when a V rise is detected. The Reset pulse will occur DD at the POR circuit threshold voltage (V nominally 1 ...
Page 128
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 19-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70118J-page 128 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2011 Microchip Technology Inc. ...
Page 129
... Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2011 Microchip Technology Inc. dsPIC30F2010 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 130
... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70118J-page 130 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2011 Microchip Technology Inc. ...
Page 131
... The Brown-out protection circuit and the Low Voltage Detect circuit, if enabled, will remain functional during Sleep. © 2011 Microchip Technology Inc. The processor wakes up from Sleep if at least one of the following conditions has occurred: • any interrupt that is individually enabled and meets the required priority level • ...
Page 132
... PGD and PGC pin functions in all dsPIC30F devices EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ EMUC3 is selected as the Debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions ( are not multiplexed with the PGD and PGC pin functions. © 2011 Microchip Technology Inc. bits ...
Page 133
TABLE 19-7: SYSTEM INTEGRATION REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR BGST — OSCCON 0742 TUN3 TUN2 COSC<1:0> Legend: — = unimplemented bit Note 1: Refer to the “dsPIC30F Family ...
Page 134
... NOTES: DS70118J-page 134 © 2011 Microchip Technology Inc. ...
Page 135
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2011 Microchip Technology Inc. Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modi- fier) or file register (specified by the value of ‘ ...
Page 136
... Moreover, double word moves require two cycles. The double word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “16-bit MCU and DSC Pro- grammer’s Reference (DS70157). Description © 2011 Microchip Technology Inc. Manual” ...
Page 137
... Y data space prefetch address register for DSP instructions Wy ∈ {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2011 Microchip Technology Inc. dsPIC30F2010 Description DS70118J-page 137 ...
Page 138
... Branch if accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear © 2011 Microchip Technology Inc Status Flags cycles Affected OA,OB,SA, C,DC,N,OV,Z ...
Page 139
... DO DO #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd © 2011 Microchip Technology Inc. dsPIC30F2010 # of Description word Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set ...
Page 140
... Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) W3: WREG © 2011 Microchip Technology Inc Status Flags cycles Affected None ...
Page 141
... SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd © 2011 Microchip Technology Inc. dsPIC30F2010 # of Description word Negate Accumulator WREG = Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W( Pop Shadow Registers Push f to Top-of-Stack (TOS) ...
Page 142
... Wn = byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws © 2011 Microchip Technology Inc Status Flags cycles Affected OA,OB,OAB, SA,SB,SAB 1 1 C,DC,N,OV,Z ...
Page 143
... PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2011 Microchip Technology Inc. 21.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 144
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2011 Microchip Technology Inc. ...
Page 145
... Microchip Technology Inc. 21.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...
Page 146
... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2011 Microchip Technology Inc. ...
Page 147
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2011 Microchip Technology Inc. (except V and MCLR) ................................................... -0. (Note 1) ...
Page 148
... Max MIPS dsPIC30F2010-20E — 20 — 15 — Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +150 °C -40 — +125 ° INT I O θ Typ Max Unit Notes 48.3 — °C/W 1 33.7 — °C — °C/W 1 © 2011 Microchip Technology Inc. ...
Page 149
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max 2 ...
Page 150
... OSC1 DD 0.128 MIPS LPRC (512 kHz) (1.8 MIPS) FRC (7.37 MHz) 4 MIPS EC mode, 4X PLL 10 MIPS EC mode, 4X PLL 20 MIPS EC mode, 8X PLL 30 MIPS EC mode, 16X PLL . DD © 2011 Microchip Technology Inc. ...
Page 151
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2011 Microchip Technology Inc. dsPIC30F2010 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 152
... PD (2) Base Power Down Current (2) Watchdog Timer Current: ΔI WDT Timer 1 w/32 kHz Crystal: ΔI ( BOR On: ΔI (2) BOR © 2011 Microchip Technology Inc. ...
Page 153
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 154
... Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode C™ mode (Device not in Brown-out Reset) © 2011 Microchip Technology Inc. ...
Page 155
... During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 156
... DD Load Condition 2 - for OSC2 Pin 464Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 ≤ +85°C for Industrial ≤ +125°C for Extended Table 22- OS31 OS31 OS41 © 2011 Microchip Technology Inc. ...
Page 157
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 158
... V = 4 ≤ +85° 3 ≤ +125° 3 ≤ +85° 4 ≤ +125° 4 ≤ +85° 3 ≤ +85° 4 ≤ +125° 4 © 2011 Microchip Technology Inc. ...
Page 159
... Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN <3:0> bits can be used to compensate for temperature drift. TABLE 22-18: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param Characteristic No. OS65A (1) LPRC @ Freq. = 512 kHz OS65B OS65C Note 1: Change of LPRC frequency as V © 2011 Microchip Technology Inc. (3) MIPs MIPs (2) (μsec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1.0 4.0 ...
Page 160
... T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1,2,3) (4) Min Typ Max — — — — — — CY Units Conditions ns — ns — ns — — — . OSC © 2011 Microchip Technology Inc. ...
Page 161
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 22-1 and Table 22-10 © 2011 Microchip Technology Inc. dsPIC30F2010 SY10 SY13 Note: Refer to Figure 22-2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 162
... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13>Status bit © 2011 Microchip Technology Inc. ...
Page 163
... SOSC1/T1CK oscillator input frequency range (oscillator enabled by setting bit TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2011 Microchip Technology Inc. Tx11 Tx10 Tx15 OS60 for load conditions. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 164
... T — — CY ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 T — — CY © 2011 Microchip Technology Inc. ...
Page 165
... TQCP Input Period Synchronous, TQ20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. dsPIC30F2010 TQ11 TQ10 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 166
... Industrial ≤ +125°C for Extended Max Units Conditions — ns — — ns — ns — — ns — prescale value (1, 4, 16) ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns See parameter DO32 ns See parameter DO31 © 2011 Microchip Technology Inc. ...
Page 167
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 168
... T (1) (2) Min Typ Max Units — — — ns — — — ns — — — — ns ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions See parameter DO32 See parameter DO31 — — © 2011 Microchip Technology Inc. ...
Page 169
... Note 1: These parameters are characterized but not tested in manufacturing Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” (DS70063) in the “dsPIC30F Family Reference Manual” (DS70046). © 2011 Microchip Technology Inc. TQ36 TQ30 TQ31 TQ35 ...
Page 170
... T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1) Min Max Units — — — CY Conditions 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) ns — © 2011 Microchip Technology Inc. ...
Page 171
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. SP10 SP21 SP20 BIT14 - - - - - -1 MSb SP30 BIT14 - - - -1 Standard Operating Conditions: 2 ...
Page 172
... Extended A Max Units Conditions — ns See Note 3 — ns See Note 3 — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — — ns — — ns — — ns — © 2011 Microchip Technology Inc. ...
Page 173
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. SP70 SP72 SP73 SP72 SP73 ...
Page 174
... SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 22-2 for load conditions. DS70118J-page 174 SP70 SP72 SP73 SP35 SP73 SP72 SP52 BIT14 - - - - - -1 LSb BIT14 - - - -1 LSb IN SP52 SP51 © 2011 Microchip Technology Inc. ...
Page 175
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...
Page 176
... C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 22-2 for load conditions. DS70118J-page 176 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 © 2011 Microchip Technology Inc. ...
Page 177
... C™ Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ C)” (DS70068) in the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I © 2011 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 178
... IS30 SDA Start Condition 2 FIGURE 22-23: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out DS70118J-page 178 IS33 IS11 IS10 IS26 IS25 IS40 IS34 Stop Condition IS21 IS33 IS45 © 2011 Microchip Technology Inc. ...
Page 179
... SDA IS50 C Bus Capacitive B Loading Note 1: Maximum pin capacitance = 10 pF for all I © 2011 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended ...
Page 180
... INL SS REFL REFH Source Impedance = 5 kΩ Ω — bits — LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH © 2011 Microchip Technology Inc. ...
Page 181
... The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 3: Measurements were taken with external V © 2011 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 182
... Section 17. “10-bit A/D Converter” (DS70064) of the ”dsPIC30F Family Reference Manual” (DS70 SAMP 3 – Software clears ADCON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One T for end of conversion. AD DS70118J-page 182 AD55 AD55 © 2011 Microchip Technology Inc. ...
Page 183
... Software sets ADCON. ADON to start AD operation. 2 – Sampling starts after discharge period Section 17. “10-bit A/D Converter” (DS70064) of the ”dsPIC30F Family Reference Manual” (DS70046). 3 – Convert bit 9. 4 – Convert bit 8. © 2011 Microchip Technology Inc. dsPIC30F2010 AD55 AD55 4 5 ...
Page 184
... T — 1 — 0.5 T — AD — — 20 ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions (1) ns See Table 18-1 ns — — — (1) See Table 18-1 (1) — See Table 18-1 ns — ns — ns — μs — © 2011 Microchip Technology Inc. ...
Page 185
... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. dsPIC30F2010 Example dsPIC30F2010 e ...
Page 186
... D TOP VIEW A3 DS70118J-page 186 EXPOSED PAD NOTE 1 BOTTOM VIEW © 2011 Microchip Technology Inc. ...
Page 187
... Microchip Technology Inc. dsPIC30F2010 DS70118J-page 187 ...
Page 188
... N NOTE DS70118J-page 188 © 2011 Microchip Technology Inc. c ...
Page 189
... D N NOTE © 2011 Microchip Technology Inc. dsPIC30F2010 α h φ β DS70118J-page 189 ...
Page 190
... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70118J-page 190 © 2011 Microchip Technology Inc. ...
Page 191
... Additional minor corrections throughout document. Revision G (December 2006) This revision includes updates to the packaging diagrams. © 2011 Microchip Technology Inc. dsPIC30F2010 Revision H (March 2008) This revision reflects these updates: • Changed the location of the input reference in the 10-bit High-Speed ADC Functional Block Diagram ...
Page 192
... System” Added the “MM” package definition. DS70118J-page 192 Update Description “Pin Diagrams”). and AV DD Equation 14-1 (FRC)”. Table 22-7). Table 22-11). (see Table 1-1). SS Table 14-1). and Equation 14-2). Section 19.2.5 “Fast RC Table 22-8). © 2011 Microchip Technology Inc. ...
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... Timing Characteristics .............................................. 162 Barrel Shifter ....................................................................... 18 Bit-Reversed Addressing .................................................... 35 Example ...................................................................... 35 Implementation ........................................................... 35 Modifier Values (Table)............................................... 36 Sequence Table (16-Entry)......................................... 36 Block Diagram PWM ........................................................................... 82 © 2011 Microchip Technology Inc. dsPIC30F2010 Block Diagrams 10-bit High Speed ADC Functional........................... 111 16-bit Timer1 Module.................................................. 58 DSP Engine ................................................................ 15 dsPIC30F2010.............................................................. 8 External Power-on Reset Circuit .............................. 129 ...
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... Input Capture (CAPx) Timing Characteristics................... 166 Input Capture Interrupts...................................................... 69 Register Map .............................................................. 70 Input Capture Module ......................................................... 67 In CPU Sleep Mode .................................................... 69 Simple Capture Event Mode....................................... 68 Input Capture Timing Requirements................................. 166 Input Change Notification Module....................................... 54 Register Map (bits 15-0) ............................................. 55 Input Characteristics QEA/QEB ................................................................. 169 © 2011 Microchip Technology Inc. ...
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... Output Compare Interrupts ................................................. 73 Output Compare Mode Register Map............................................................... 74 Output Compare Module..................................................... 71 Timing Characteristics .............................................. 166 Timing Requirements................................................ 166 © 2011 Microchip Technology Inc. dsPIC30F2010 Output Compare Operation During CPU Idle Mode ........... 73 Output Compare Sleep Mode Operation ............................ 73 P Packaging Information ...................................................... 185 Marking..................................................................... 185 Pinout Descriptions ...
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... Real-Time Clock ......................................................... 59 RTC Interrupts .................................................... 59 RTC Oscillator Operation ................................... 59 Register Map .............................................................. 60 Timer2 and Timer3 Selection Mode.................................... 72 Timer2/3 Module................................................................. 61 32-bit Synchronous Counter Mode ............................. 61 32-bit Timer Mode....................................................... 61 ADC Event Trigger...................................................... 64 Gate Operation ........................................................... 64 Interrupt ...................................................................... 64 Operation During Sleep Mode .................................... 64 Register Map .............................................................. 65 Timer Prescaler .......................................................... 64 © 2011 Microchip Technology Inc. ...
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... Motor Control PWM Module...................................... 168 Oscillator Start-up Timer ........................................... 161 Output Compare Module........................................... 166 Power-up Timer ........................................................ 161 QEI Module External Clock................................................... 165 Index Pulse ....................................................... 170 © 2011 Microchip Technology Inc. dsPIC30F2010 Quadrature Decoder................................................. 169 Reset ........................................................................ 161 Simple OC/PWM Mode ............................................ 167 SPI Module Master Mode (CKE = 0).................................... 171 Master Mode (CKE = 1) ...
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... NOTES: DS70118J-page 198 © 2011 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com. Under “Support”, “Customer Change Notification” and follow the registration instructions. © 2011 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70118J-page 200 FAX: (______) _________ - _________ N Total Pages Sent ________ Literature Number: DS70118J © 2011 Microchip Technology Inc. ...