ATMEGA324PA-CUR Atmel, ATMEGA324PA-CUR Datasheet - Page 23

• Manufacturer Part Number: ATMEGA324PA-CUR
• Description: MCU AVR 32KB FLSH 20 MHZ 49VFBGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324PA-CUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
8152G–AVR–11/09
I/O Memory
The I/O space definition of the ATmega164PA/324PA/644PA/1284P is shown in
mary” on page
All ATmega164PA/324PA/644PA/1284P I/Os and peripherals are placed in the I/O space. All
I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring
data between the 32 general purpose working registers and the I/O space. I/O Registers within
the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data
space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega164PA/324PA/644PA/1284P is a complex microcontroller with more peripheral units
than can be supported within the 64 location reserved in Opcode for the IN and OUT instruc-
tions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega164PA/324PA/644PA/1284P contains three General Purpose I/O Registers, see
”Register Description” on page
they are particularly useful for storing global variables and Status Flags. General Purpose I/O
Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI,
SBIS, and SBIC instructions.
442.
ATmega164PA/324PA/644PA/1284P
24. These registers can be used for storing any information, and
”Register Sum-
23