AT91SAM7S161-AU Atmel, AT91SAM7S161-AU Datasheet - Page 481
![IC MCU ARM7 16KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT91SAM7S161-AU
Manufacturer Part Number
AT91SAM7S161-AU
Description
IC MCU ARM7 16KB FLASH 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S161-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S161-AU
Manufacturer:
NXP
Quantity:
3
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6175K–ATARM–30-Aug-10
Figure 34-4. Non Overlapped Center Aligned Waveforms
Note:
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
(
-------------------------------------------- -
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
(
--------------------------------------------
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
(
-------------------------------------------------------
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
CRPD
2
2
PWM0
PWM1
duty cycle
duty cycle
×
×
X
CPRD
See
MCK
MCK
×
MCK
×
CPRD
Figure 34-5 on page 483
DIVA
×
=
=
DIVA
No overlap
)
)
(
------------------------------------------------------------------------------------------------------------- -
(
-------------------------------------------------------------------------------------------------------------------------------- -
period 1
(
or
period
)
(
------------------------------------------------ -
CRPD
or
Period
(
-------------------------------------------------------
–
2
⁄
MCK
×
×
2
⁄
CPRD
) 1
DIVAB
fchannel_x_clock
–
MCK
for a detailed description of center aligned waveforms.
AT91SAM7S Series Preliminary
period
⁄
(
×
period
)
fchannel_x_clock
DIVB
)
⁄
2
)
×
CDTY
×
CDTY
)
) )
481
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