PIC16C72A-20/SO Microchip Technology, PIC16C72A-20/SO Datasheet - Page 14
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PIC16C72A-20/SO
Manufacturer Part Number
PIC16C72A-20/SO
Description
IC MCU OTP 2KX14 A/D PWM 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C62B-04SO.pdf
(120 pages)
4.PIC16C72A-04SP.pdf
(6 pages)
Specifications of PIC16C72A-20/SO
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Interface
I2C, SPI
Embedded Interface Type
I2C, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16C72A-20/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16C62B/72A
2.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4:
DS35008B-page 14
bit7
bit 7:
bit 6:
bit 5-4: Unimplemented: Read as ‘0’
bit 3:
bit 2:
bit 1:
bit 0:
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this
U-0
—
PIE1 REGISTER
Unimplemented: Read as ‘0’
ADIE
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
bit clear.
ADIE
R/W-0
(1)
(1)
: A/D Converter Interrupt Enable bit
PIE1 REGISTER (ADDRESS 8Ch)
U-0
—
U-0
—
SSPIE
R/W-0
Preliminary
CCP1IE
R/W-0
TMR2IE
R/W-0
Note:
TMR1IE
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
1999 Microchip Technology Inc.
read as ‘0’