PIC18LF45K22-I/PT Microchip Technology, PIC18LF45K22-I/PT Datasheet - Page 93
![MCU 8BIT 32KB FLASH 3.6V 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF45K22-I/PT
Manufacturer Part Number
PIC18LF45K22-I/PT
Description
MCU 8BIT 32KB FLASH 3.6V 44TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF45K22-I/PT
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
1536Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 28 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF45K22-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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FIGURE 5-11:
2010 Microchip Technology Inc.
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations
(Bank 15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a’ = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
F60h
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
to
FFFh
Preliminary
FFFh
FFFh
F00h
F60h
FFFh
000h
060h
100h
F00h
F60h
000h
060h
100h
F00h
F60h
000h
060h
100h
Data Memory
Data Memory
Data Memory
Bank 15
Bank 15
Bank 15
Bank 14
Bank 14
Bank 14
Bank 0
through
Bank 0
through
Bank 0
through
Bank 1
Bank 1
Bank 1
SFRs
SFRs
SFRs
PIC18(L)F2X/4XK22
001001da
00000000
001001da
BSR
Access RAM
FSR2H
ffffffff
ffffffff
FSR2L
00h
60h
FFh
DS41412D-page 93
Valid range
for ‘f’
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