PIC18LF45K22-I/PT Microchip Technology, PIC18LF45K22-I/PT Datasheet - Page 391
![MCU 8BIT 32KB FLASH 3.6V 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF45K22-I/PT
Manufacturer Part Number
PIC18LF45K22-I/PT
Description
MCU 8BIT 32KB FLASH 3.6V 44TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF45K22-I/PT
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
1536Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 28 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF45K22-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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LFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2010 Microchip Technology Inc.
Q Cycle Activity:
After Instruction
Decode
Decode
FSR2H
FSR2L
Q1
Read literal
Read literal
Load FSR
LFSR f, k
0 f 2
0 k 4095
k FSRf
None
File Select Register pointed to by ‘f’.
2
2
The 12-bit literal ‘k’ is loaded into the
‘k’ MSB
‘k’ LSB
LFSR 2, 3ABh
1110
1111
Q2
=
=
03h
ABh
1110
0000
Process
Process
Data
Data
Q3
k
00ff
7
kkk
‘k’ to FSRfL
Write literal
literal ‘k’
MSB to
FSRfH
Write
k
Q4
kkkk
11
kkk
Preliminary
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
Decode
REG
W
REG
W
Q1
register ‘f’
Move f
MOVF
0 f 255
d [0,1]
a [0,1]
f dest
N, Z
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
MOVF
Read
0101
Q2
=
=
=
=
22h
FFh
22h
22h
f {,d {,a}}
REG, 0, 0
00da
Process
Data
Q3
DS41412D-page 391
ffff
for details.
Write W
Q4
ffff
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