DSPIC30F2011-20E/ML Microchip Technology, DSPIC30F2011-20E/ML Datasheet - Page 10
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DSPIC30F2011-20E/ML
Manufacturer Part Number
DSPIC30F2011-20E/ML
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011-20E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
DAF30-4 - DEVICE ATP FOR ICE4000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
dsPIC30F2011/2012
11. Module: Timer
12. Module: PLL
DS80450D-page 10
When the timer is being operated in Asynchronous
mode using the secondary oscillator (32.768 kHz)
and the device is put into Sleep mode, a clock
switch to any other oscillator mode before putting
the device to Sleep prevents the timer from waking
the device from Sleep.
Work around
Do not clock switch to any other oscillator mode if
the timer is being used in Asynchronous mode
using the secondary oscillator (32.768 kHz).
Affected Silicon Revisions
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
Work around
The user application must include an oscillator
failure trap service routine. In the trap service
routine, first inspect the status of the Clock Failure
Status bit (OSCCON<3>). If this bit is clear, return
from the trap service routine immediately and
continue program execution.
Affected Silicon Revisions
A1
A1
X
X
13. Module: PSV Operations
14. Module: I/O
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
Program Space Visibility (PSV) page. This only
occurs when using the following addressing
modes:
• MOV.D
• Register Indirect Addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
Affected Silicon Revisions
If the user application enables the auto-baud
feature in the UART module, the I/O pin
multiplexed with the IC1 (Input Capture) pin cannot
be used as a digital input. However, the external
interrupt function (INT1) can be used.
Work around
None.
Affected Silicon Revisions
A1
A1
mode) with pre/post-decrement
X
X
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