PIC16LC770-E/SS Microchip Technology, PIC16LC770-E/SS Datasheet - Page 19
PIC16LC770-E/SS
Manufacturer Part Number
PIC16LC770-E/SS
Description
IC MCU OTP 2KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC770-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LC770E/SS
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
PIC16LC770-E/SS
Manufacturer:
MICROCHIP
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4 000
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2.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4:
2002 Microchip Technology Inc.
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
PIE1 REGISTER
PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1: 8Ch)
Unimplemented: Read as ’0’
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
Unimplemented: Read as ’0’
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
bit 7
Legend:
R = Readable bit
- n = Value at POR
U-0
—
R/W-0
ADIE
U-0
—
W = Writable bit
’1’ = Bit is set
U-0
—
Note:
PIC16C717/770/771
SSPIE
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
CCP1IE
R/W-0
x = Bit is unknown
TMR2IE
R/W-0
DS41120B-page 17
TMR1IE
R/W-0
bit 0
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