ATMEGA164PA-MCH Atmel, ATMEGA164PA-MCH Datasheet - Page 112
![MCU AVR 16KB FLASH 20MHZ 44-VQFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA164PA-MCH
Manufacturer Part Number
ATMEGA164PA-MCH
Description
MCU AVR 16KB FLASH 20MHZ 44-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA164PA-MCH
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15. 16-bit Timer/Counter1 with PWM
15.1
15.2
8272A–AVR–01/10
Features
Overview
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement.
Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
placement of I/O pins, see
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the
The PRTIM1 bit in
enable Timer/Counter1 module.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
True 16-bit Design (i.e., Allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
”Register Description” on page
”PRR – Power Reduction Register” on page 49
”Pin Configurations” on page
133.
2. CPU accessible I/O Registers, includ-
Figure
must be written to zero to
15-1. For the actual
112
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