PIC16LF627A-I/ML Microchip Technology, PIC16LF627A-I/ML Datasheet - Page 15

• Manufacturer Part Number: PIC16LF627A-I/ML
• Description: IC MCU FLASH 1KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF627A-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

3.1
The clock input (RA7/OSC1/CLKIN pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4.
Internally, the Program Counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
FIGURE 3-2:
EXAMPLE 3-1:
© 2009 Microchip Technology Inc.
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
4. BSF
CLKOUT
OSC1
Note:
PC
Q1
Q2
Q3
Q4
Clocking Scheme/Instruction
Cycle
SUB_1
PORTA, 3
Q1
All instructions are single cycle except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
Execute INST (PC - 1)
Fetch INST (PC)
Q2
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
PC
Q3
Fetch 1
Q4
Execute 1
Fetch 2
Q1
Execute INST (PC)
Fetch INST (PC + 1)
Q2
PIC16F627A/628A/648A
Execute 2
PC + 1
Fetch 3
Q3
3.2
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q4
Execute 3
Fetch 4
Instruction Flow/Pipelining
Q1
Execute INST (PC + 1)
Fetch SUB_1 Execute SUB_1
Fetch INST (PC + 2)
Q2
Flush
PC + 2
Q3
DS40044G-page 15
Q4
Internal
phase
clock